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ASoC: nau8825: support different clock source for FLL function 

Extend FLL clock source selection. The source can be from MCLK, BCLK or FS.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
John Hsu 2016-03-15 12:08:21 +08:00 committed by Mark Brown
parent 1a695a905c
commit 70543c3009
2 changed files with 67 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

82
sound/soc/codecs/nau8825.c
View File

@ -1069,6 +1069,37 @@ static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
return 0; return 0;
} }
static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
{
int ret = 0;
nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
if (IS_ERR(nau8825->mclk)) {
dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
return 0;
}
if (!nau8825->mclk_freq) {
ret = clk_prepare_enable(nau8825->mclk);
if (ret) {
dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
return ret;
}
}
if (nau8825->mclk_freq != freq) {
freq = clk_round_rate(nau8825->mclk, freq);
ret = clk_set_rate(nau8825->mclk, freq);
if (ret) {
dev_err(nau8825->dev, "Unable to set mclk rate\n");
return ret;
}
nau8825->mclk_freq = freq;
}
return 0;
}
static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
unsigned int freq) unsigned int freq)
{ {
@ -1080,29 +1111,9 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK); NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 0); regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
ret = nau8825_mclk_prepare(nau8825, freq);
/* We selected MCLK source but the clock itself managed externally */ if (ret)
if (!nau8825->mclk) return ret;
break;
if (!nau8825->mclk_freq) {
ret = clk_prepare_enable(nau8825->mclk);
if (ret) {
dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
return ret;
}
}
if (nau8825->mclk_freq != freq) {
nau8825->mclk_freq = freq;
freq = clk_round_rate(nau8825->mclk, freq);
ret = clk_set_rate(nau8825->mclk, freq);
if (ret) {
dev_err(nau8825->dev, "Unable to set mclk rate\n");
return ret;
}
}
break; break;
case NAU8825_CLK_INTERNAL: case NAU8825_CLK_INTERNAL:
@ -1110,7 +1121,32 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
NAU8825_DCO_EN); NAU8825_DCO_EN);
regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
if (nau8825->mclk_freq) {
clk_disable_unprepare(nau8825->mclk);
nau8825->mclk_freq = 0;
}
break;
case NAU8825_CLK_FLL_MCLK:
regmap_update_bits(regmap, NAU8825_REG_FLL3,
NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_MCLK);
ret = nau8825_mclk_prepare(nau8825, freq);
if (ret)
return ret;
break;
case NAU8825_CLK_FLL_BLK:
regmap_update_bits(regmap, NAU8825_REG_FLL3,
NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_BLK);
if (nau8825->mclk_freq) {
clk_disable_unprepare(nau8825->mclk);
nau8825->mclk_freq = 0;
}
break;
case NAU8825_CLK_FLL_FS:
regmap_update_bits(regmap, NAU8825_REG_FLL3,
NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_FS);
if (nau8825->mclk_freq) { if (nau8825->mclk_freq) {
clk_disable_unprepare(nau8825->mclk); clk_disable_unprepare(nau8825->mclk);
nau8825->mclk_freq = 0; nau8825->mclk_freq = 0;

8
sound/soc/codecs/nau8825.h
View File

@ -113,6 +113,11 @@
/* FLL3 (0x06) */ /* FLL3 (0x06) */
#define NAU8825_FLL_INTEGER_MASK (0x3ff << 0) #define NAU8825_FLL_INTEGER_MASK (0x3ff << 0)
#define NAU8825_FLL_CLK_SRC_SFT 10
#define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT)
#define NAU8825_FLL_CLK_SRC_MCLK (0 << NAU8825_FLL_CLK_SRC_SFT)
#define NAU8825_FLL_CLK_SRC_BLK (0x2 << NAU8825_FLL_CLK_SRC_SFT)
#define NAU8825_FLL_CLK_SRC_FS (0x3 << NAU8825_FLL_CLK_SRC_SFT)
/* FLL4 (0x07) */ /* FLL4 (0x07) */
#define NAU8825_FLL_REF_DIV_MASK (0x3 << 10) #define NAU8825_FLL_REF_DIV_MASK (0x3 << 10)
@ -320,6 +325,9 @@
enum { enum {
NAU8825_CLK_MCLK = 0, NAU8825_CLK_MCLK = 0,
NAU8825_CLK_INTERNAL, NAU8825_CLK_INTERNAL,
NAU8825_CLK_FLL_MCLK,
NAU8825_CLK_FLL_BLK,
NAU8825_CLK_FLL_FS,
}; };
struct nau8825 { struct nau8825 {