unicore32 machine related files: pci bus handling
This patch implements arch-specific pci bus driver. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
This commit is contained in:
GuanXuetao
parent
b08b4f8e63
commit
700598cef8
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@ -0,0 +1,46 @@
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/*
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* linux/arch/unicore32/include/asm/pci.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_PCI_H__
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#define __UNICORE_PCI_H__
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#ifdef __KERNEL__
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#include <asm-generic/pci-dma-compat.h>
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#include <asm-generic/pci.h>
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#include <mach/hardware.h> /* for PCIBIOS_MIN_* */
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static inline void pcibios_set_master(struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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static inline void pcibios_penalize_isa_irq(int irq, int active)
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{
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/* We don't do dynamic PCI IRQ allocation */
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}
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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*strat = PCI_DMA_BURST_INFINITY;
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*strategy_parameter = ~0UL;
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}
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#endif
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#define HAVE_PCI_MMAP
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extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine);
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#endif /* __KERNEL__ */
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#endif
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@ -0,0 +1,404 @@
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/*
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* linux/arch/unicore32/kernel/pci.c
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* PCI bios-type initialisation for PCI machines
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/io.h>
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static int debug_pci;
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static int use_firmware;
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#define CONFIG_CMD(bus, devfn, where) \
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(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
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static int
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puv3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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PCICFG_ADDR = CONFIG_CMD(bus, devfn, where);
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switch (size) {
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case 1:
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*value = (PCICFG_DATA >> ((where & 3) * 8)) & 0xFF;
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break;
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case 2:
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*value = (PCICFG_DATA >> ((where & 2) * 8)) & 0xFFFF;
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break;
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case 4:
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*value = PCICFG_DATA;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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puv3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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PCICFG_ADDR = CONFIG_CMD(bus, devfn, where);
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switch (size) {
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case 1:
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PCICFG_DATA = (PCICFG_DATA & ~FMASK(8, (where&3)*8))
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| FIELD(value, 8, (where&3)*8);
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break;
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case 2:
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PCICFG_DATA = (PCICFG_DATA & ~FMASK(16, (where&2)*8))
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| FIELD(value, 16, (where&2)*8);
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break;
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case 4:
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PCICFG_DATA = value;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops pci_puv3_ops = {
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.read = puv3_read_config,
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.write = puv3_write_config,
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};
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void pci_puv3_preinit(void)
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{
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printk(KERN_DEBUG "PCI: PKUnity PCI Controller Initializing ...\n");
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/* config PCI bridge base */
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PCICFG_BRIBASE = PKUNITY_PCIBRI_BASE;
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PCIBRI_AHBCTL0 = 0;
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PCIBRI_AHBBAR0 = PKUNITY_PCIBRI_BASE | PCIBRI_BARx_MEM;
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PCIBRI_AHBAMR0 = 0xFFFF0000;
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PCIBRI_AHBTAR0 = 0;
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PCIBRI_AHBCTL1 = PCIBRI_CTLx_AT;
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PCIBRI_AHBBAR1 = PKUNITY_PCILIO_BASE | PCIBRI_BARx_IO;
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PCIBRI_AHBAMR1 = 0xFFFF0000;
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PCIBRI_AHBTAR1 = 0x00000000;
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PCIBRI_AHBCTL2 = PCIBRI_CTLx_PREF;
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PCIBRI_AHBBAR2 = PKUNITY_PCIMEM_BASE | PCIBRI_BARx_MEM;
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PCIBRI_AHBAMR2 = 0xF8000000;
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PCIBRI_AHBTAR2 = 0;
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PCIBRI_BAR1 = PKUNITY_PCIAHB_BASE | PCIBRI_BARx_MEM;
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PCIBRI_PCICTL0 = PCIBRI_CTLx_AT | PCIBRI_CTLx_PREF;
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PCIBRI_PCIBAR0 = PKUNITY_PCIAHB_BASE | PCIBRI_BARx_MEM;
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PCIBRI_PCIAMR0 = 0xF8000000;
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PCIBRI_PCITAR0 = PKUNITY_SDRAM_BASE;
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PCIBRI_CMD = PCIBRI_CMD | PCIBRI_CMD_IO | PCIBRI_CMD_MEM;
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}
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static int __init pci_puv3_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (dev->bus->number == 0) {
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#ifdef CONFIG_ARCH_FPGA /* 4 pci slots */
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if (dev->devfn == 0x00)
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return IRQ_PCIINTA;
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else if (dev->devfn == 0x08)
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return IRQ_PCIINTB;
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else if (dev->devfn == 0x10)
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return IRQ_PCIINTC;
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else if (dev->devfn == 0x18)
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return IRQ_PCIINTD;
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#endif
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#ifdef CONFIG_PUV3_DB0913 /* 3 pci slots */
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if (dev->devfn == 0x30)
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return IRQ_PCIINTB;
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else if (dev->devfn == 0x60)
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return IRQ_PCIINTC;
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else if (dev->devfn == 0x58)
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return IRQ_PCIINTD;
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#endif
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#if defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919)
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/* only support 2 pci devices */
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if (dev->devfn == 0x00)
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return IRQ_PCIINTC; /* sata */
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#endif
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}
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return -1;
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}
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/*
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* Only first 128MB of memory can be accessed via PCI.
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* We use GFP_DMA to allocate safe buffers to do map/unmap.
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* This is really ugly and we need a better way of specifying
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* DMA-capable regions of memory.
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*/
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void __init puv3_pci_adjust_zones(unsigned long *zone_size,
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unsigned long *zhole_size)
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{
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unsigned int sz = SZ_128M >> PAGE_SHIFT;
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/*
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* Only adjust if > 128M on current system
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*/
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if (zone_size[0] <= sz)
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return;
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zone_size[1] = zone_size[0] - sz;
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zone_size[0] = sz;
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zhole_size[1] = zhole_size[0];
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zhole_size[0] = 0;
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}
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void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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if (debug_pci)
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printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n",
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irq, pci_name(dev));
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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/*
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* If the bus contains any of these devices, then we must not turn on
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* parity checking of any kind.
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*/
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static inline int pdev_bad_for_parity(struct pci_dev *dev)
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{
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return 0;
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}
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/*
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* pcibios_fixup_bus - Called after each bus is probed,
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* but before its children are examined.
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*/
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void __devinit pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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u16 features = PCI_COMMAND_SERR
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| PCI_COMMAND_PARITY
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| PCI_COMMAND_FAST_BACK;
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bus->resource[0] = &ioport_resource;
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bus->resource[1] = &iomem_resource;
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/*
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* Walk the devices on this bus, working out what we can
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* and can't support.
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*/
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 status;
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pci_read_config_word(dev, PCI_STATUS, &status);
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/*
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* If any device on this bus does not support fast back
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* to back transfers, then the bus as a whole is not able
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* to support them. Having fast back to back transfers
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* on saves us one PCI cycle per transaction.
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*/
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if (!(status & PCI_STATUS_FAST_BACK))
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features &= ~PCI_COMMAND_FAST_BACK;
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if (pdev_bad_for_parity(dev))
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features &= ~(PCI_COMMAND_SERR
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| PCI_COMMAND_PARITY);
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switch (dev->class >> 8) {
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case PCI_CLASS_BRIDGE_PCI:
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
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status |= PCI_BRIDGE_CTL_PARITY
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| PCI_BRIDGE_CTL_MASTER_ABORT;
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status &= ~(PCI_BRIDGE_CTL_BUS_RESET
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| PCI_BRIDGE_CTL_FAST_BACK);
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
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break;
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case PCI_CLASS_BRIDGE_CARDBUS:
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pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL,
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&status);
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status |= PCI_CB_BRIDGE_CTL_PARITY
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| PCI_CB_BRIDGE_CTL_MASTER_ABORT;
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pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL,
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status);
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break;
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}
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}
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/*
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* Now walk the devices again, this time setting them up.
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*/
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 cmd;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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cmd |= features;
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
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L1_CACHE_BYTES >> 2);
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}
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/*
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* Propagate the flags to the PCI bridge.
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*/
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if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
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if (features & PCI_COMMAND_FAST_BACK)
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bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
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if (features & PCI_COMMAND_PARITY)
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bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
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}
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/*
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* Report what we did for this bus
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*/
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printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
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bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
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}
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#ifdef CONFIG_HOTPLUG
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EXPORT_SYMBOL(pcibios_fixup_bus);
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#endif
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static int __init pci_common_init(void)
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{
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struct pci_bus *puv3_bus;
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pci_puv3_preinit();
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puv3_bus = pci_scan_bus(0, &pci_puv3_ops, NULL);
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if (!puv3_bus)
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panic("PCI: unable to scan bus!");
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pci_fixup_irqs(pci_common_swizzle, pci_puv3_map_irq);
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if (!use_firmware) {
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/*
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* Size the bridge windows.
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*/
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pci_bus_size_bridges(puv3_bus);
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/*
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* Assign resources.
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*/
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pci_bus_assign_resources(puv3_bus);
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}
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/*
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* Tell drivers about devices found.
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*/
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pci_bus_add_devices(puv3_bus);
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return 0;
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}
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subsys_initcall(pci_common_init);
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char * __devinit pcibios_setup(char *str)
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{
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if (!strcmp(str, "debug")) {
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debug_pci = 1;
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return NULL;
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} else if (!strcmp(str, "firmware")) {
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use_firmware = 1;
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return NULL;
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}
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return str;
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}
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/*
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* From arch/i386/kernel/pci-i386.c:
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*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might be mirrored at 0x0100-0x03ff..
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO && start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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start = (start + align - 1) & ~(align - 1);
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return start;
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}
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/**
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* pcibios_enable_device - Enable I/O and memory.
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* @dev: PCI device to be enabled
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*/
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for (idx = 0; idx < 6; idx++) {
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/* Only set up the requested stuff */
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if (!(mask & (1 << idx)))
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continue;
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r = dev->resource + idx;
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if (!r->start && r->end) {
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printk(KERN_ERR "PCI: Device %s not available because"
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" of resource collisions\n", pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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/*
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* Bridges (eg, cardbus bridges) need to be fully enabled
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*/
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if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
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cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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if (cmd != old_cmd) {
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printk("PCI: enabling device %s (%04x -> %04x)\n",
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pci_name(dev), old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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unsigned long phys;
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if (mmap_state == pci_mmap_io)
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return -EINVAL;
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phys = vma->vm_pgoff;
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/*
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* Mark this as IO
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*/
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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if (remap_pfn_range(vma, vma->vm_start, phys,
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vma->vm_end - vma->vm_start,
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vma->vm_page_prot))
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return -EAGAIN;
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return 0;
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}
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@ -42,6 +42,7 @@ obj-$(CONFIG_PCI_IOV) += iov.o
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obj-$(CONFIG_X86) += setup-bus.o
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obj-$(CONFIG_ALPHA) += setup-bus.o setup-irq.o
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obj-$(CONFIG_ARM) += setup-bus.o setup-irq.o
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obj-$(CONFIG_UNICORE32) += setup-bus.o setup-irq.o
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obj-$(CONFIG_PARISC) += setup-bus.o
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obj-$(CONFIG_SUPERH) += setup-bus.o setup-irq.o
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obj-$(CONFIG_PPC) += setup-bus.o
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