clk: berlin: add driver for BG2x complex divider cells
This is a driver for the complex divider cells found on Marvell Berlin2 SoCs. The cells come in two flavors: single register cells and shared register cells. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Alexandre Belloni
Mike Turquette
parent
cf8de5a7f8
commit
6f9ba9b447
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obj-y += berlin2-avpll.o berlin2-pll.o
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obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
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/*
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* Copyright (c) 2014 Marvell Technology Group Ltd.
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*
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* Alexandre Belloni <alexandre.belloni@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "berlin2-div.h"
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/*
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* Clock dividers in Berlin2 SoCs comprise a complex cell to select
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* input pll and divider. The virtual structure as it is used in Marvell
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* BSP code can be seen as:
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*
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* +---+
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* pll0 --------------->| 0 | +---+
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* +---+ |(B)|--+--------------->| 0 | +---+
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* pll1.0 -->| 0 | +-->| 1 | | +--------+ |(E)|----->| 0 | +---+
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* pll1.1 -->| 1 | | +---+ +-->|(C) 1:M |-->| 1 | |(F)|-->|(G)|->
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* ... -->|(A)|--+ | +--------+ +---+ +-->| 1 | +---+
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* ... -->| | +-->|(D) 1:3 |----------+ +---+
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* pll1.N -->| N | +---------
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* +---+
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*
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* (A) input pll clock mux controlled by <PllSelect[1:n]>
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* (B) input pll bypass mux controlled by <PllSwitch>
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* (C) programmable clock divider controlled by <Select[1:n]>
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* (D) constant div-by-3 clock divider
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* (E) programmable clock divider bypass controlled by <Switch>
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* (F) constant div-by-3 clock mux controlled by <D3Switch>
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* (G) clock gate controlled by <Enable>
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*
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* For whatever reason, above control signals come in two flavors:
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* - single register dividers with all bits in one register
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* - shared register dividers with bits spread over multiple registers
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* (including signals for the same cell spread over consecutive registers)
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*
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* Also, clock gate and pll mux is not available on every div cell, so
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* we have to deal with those, too. We reuse common clock composite driver
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* for it.
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*/
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#define PLL_SELECT_MASK 0x7
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#define DIV_SELECT_MASK 0x7
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struct berlin2_div {
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struct clk_hw hw;
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void __iomem *base;
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struct berlin2_div_map map;
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spinlock_t *lock;
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};
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#define to_berlin2_div(hw) container_of(hw, struct berlin2_div, hw)
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static u8 clk_div[] = { 1, 2, 4, 6, 8, 12, 1, 1 };
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static int berlin2_div_is_enabled(struct clk_hw *hw)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 reg;
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if (div->lock)
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spin_lock(div->lock);
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reg = readl_relaxed(div->base + map->gate_offs);
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reg >>= map->gate_shift;
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if (div->lock)
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spin_unlock(div->lock);
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return (reg & 0x1);
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}
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static int berlin2_div_enable(struct clk_hw *hw)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 reg;
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if (div->lock)
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spin_lock(div->lock);
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reg = readl_relaxed(div->base + map->gate_offs);
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reg |= BIT(map->gate_shift);
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writel_relaxed(reg, div->base + map->gate_offs);
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if (div->lock)
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spin_unlock(div->lock);
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return 0;
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}
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static void berlin2_div_disable(struct clk_hw *hw)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 reg;
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if (div->lock)
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spin_lock(div->lock);
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reg = readl_relaxed(div->base + map->gate_offs);
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reg &= ~BIT(map->gate_shift);
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writel_relaxed(reg, div->base + map->gate_offs);
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if (div->lock)
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spin_unlock(div->lock);
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}
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static int berlin2_div_set_parent(struct clk_hw *hw, u8 index)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 reg;
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if (div->lock)
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spin_lock(div->lock);
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/* index == 0 is PLL_SWITCH */
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reg = readl_relaxed(div->base + map->pll_switch_offs);
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if (index == 0)
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reg &= ~BIT(map->pll_switch_shift);
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else
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reg |= BIT(map->pll_switch_shift);
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writel_relaxed(reg, div->base + map->pll_switch_offs);
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/* index > 0 is PLL_SELECT */
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if (index > 0) {
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reg = readl_relaxed(div->base + map->pll_select_offs);
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reg &= ~(PLL_SELECT_MASK << map->pll_select_shift);
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reg |= (index - 1) << map->pll_select_shift;
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writel_relaxed(reg, div->base + map->pll_select_offs);
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}
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if (div->lock)
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spin_unlock(div->lock);
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return 0;
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}
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static u8 berlin2_div_get_parent(struct clk_hw *hw)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 reg;
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u8 index = 0;
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if (div->lock)
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spin_lock(div->lock);
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/* PLL_SWITCH == 0 is index 0 */
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reg = readl_relaxed(div->base + map->pll_switch_offs);
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reg &= BIT(map->pll_switch_shift);
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if (reg) {
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reg = readl_relaxed(div->base + map->pll_select_offs);
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reg >>= map->pll_select_shift;
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reg &= PLL_SELECT_MASK;
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index = 1 + reg;
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}
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if (div->lock)
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spin_unlock(div->lock);
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return index;
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}
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static unsigned long berlin2_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct berlin2_div *div = to_berlin2_div(hw);
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struct berlin2_div_map *map = &div->map;
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u32 divsw, div3sw, divider = 1;
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if (div->lock)
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spin_lock(div->lock);
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divsw = readl_relaxed(div->base + map->div_switch_offs) &
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(1 << map->div_switch_shift);
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div3sw = readl_relaxed(div->base + map->div3_switch_offs) &
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(1 << map->div3_switch_shift);
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/* constant divide-by-3 (dominant) */
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if (div3sw != 0) {
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divider = 3;
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/* divider can be bypassed with DIV_SWITCH == 0 */
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} else if (divsw == 0) {
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divider = 1;
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/* clock divider determined by DIV_SELECT */
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} else {
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u32 reg;
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reg = readl_relaxed(div->base + map->div_select_offs);
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reg >>= map->div_select_shift;
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reg &= DIV_SELECT_MASK;
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divider = clk_div[reg];
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}
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if (div->lock)
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spin_unlock(div->lock);
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return parent_rate / divider;
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}
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static const struct clk_ops berlin2_div_rate_ops = {
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.recalc_rate = berlin2_div_recalc_rate,
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};
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static const struct clk_ops berlin2_div_gate_ops = {
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.is_enabled = berlin2_div_is_enabled,
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.enable = berlin2_div_enable,
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.disable = berlin2_div_disable,
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};
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static const struct clk_ops berlin2_div_mux_ops = {
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.set_parent = berlin2_div_set_parent,
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.get_parent = berlin2_div_get_parent,
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};
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struct clk * __init
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berlin2_div_register(const struct berlin2_div_map *map,
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void __iomem *base, const char *name, u8 div_flags,
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const char **parent_names, int num_parents,
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unsigned long flags, spinlock_t *lock)
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{
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const struct clk_ops *mux_ops = &berlin2_div_mux_ops;
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const struct clk_ops *rate_ops = &berlin2_div_rate_ops;
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const struct clk_ops *gate_ops = &berlin2_div_gate_ops;
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struct berlin2_div *div;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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/* copy div_map to allow __initconst */
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memcpy(&div->map, map, sizeof(*map));
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div->base = base;
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div->lock = lock;
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if ((div_flags & BERLIN2_DIV_HAS_GATE) == 0)
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gate_ops = NULL;
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if ((div_flags & BERLIN2_DIV_HAS_MUX) == 0)
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mux_ops = NULL;
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return clk_register_composite(NULL, name, parent_names, num_parents,
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&div->hw, mux_ops, &div->hw, rate_ops,
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&div->hw, gate_ops, flags);
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}
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@ -0,0 +1,89 @@
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/*
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* Copyright (c) 2014 Marvell Technology Group Ltd.
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*
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* Alexandre Belloni <alexandre.belloni@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __BERLIN2_DIV_H
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#define __BERLIN2_DIV_H
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struct clk;
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#define BERLIN2_DIV_HAS_GATE BIT(0)
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#define BERLIN2_DIV_HAS_MUX BIT(1)
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#define BERLIN2_PLL_SELECT(_off, _sh) \
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.pll_select_offs = _off, \
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.pll_select_shift = _sh
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#define BERLIN2_PLL_SWITCH(_off, _sh) \
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.pll_switch_offs = _off, \
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.pll_switch_shift = _sh
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#define BERLIN2_DIV_SELECT(_off, _sh) \
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.div_select_offs = _off, \
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.div_select_shift = _sh
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#define BERLIN2_DIV_SWITCH(_off, _sh) \
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.div_switch_offs = _off, \
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.div_switch_shift = _sh
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#define BERLIN2_DIV_D3SWITCH(_off, _sh) \
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.div3_switch_offs = _off, \
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.div3_switch_shift = _sh
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#define BERLIN2_DIV_GATE(_off, _sh) \
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.gate_offs = _off, \
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.gate_shift = _sh
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#define BERLIN2_SINGLE_DIV(_off) \
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BERLIN2_DIV_GATE(_off, 0), \
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BERLIN2_PLL_SELECT(_off, 1), \
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BERLIN2_PLL_SWITCH(_off, 4), \
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BERLIN2_DIV_SWITCH(_off, 5), \
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BERLIN2_DIV_D3SWITCH(_off, 6), \
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BERLIN2_DIV_SELECT(_off, 7)
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struct berlin2_div_map {
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u16 pll_select_offs;
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u16 pll_switch_offs;
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u16 div_select_offs;
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u16 div_switch_offs;
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u16 div3_switch_offs;
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u16 gate_offs;
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u8 pll_select_shift;
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u8 pll_switch_shift;
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u8 div_select_shift;
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u8 div_switch_shift;
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u8 div3_switch_shift;
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u8 gate_shift;
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};
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struct berlin2_div_data {
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const char *name;
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const u8 *parent_ids;
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int num_parents;
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unsigned long flags;
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struct berlin2_div_map map;
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u8 div_flags;
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};
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struct clk * __init
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berlin2_div_register(const struct berlin2_div_map *map,
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void __iomem *base, const char *name, u8 div_flags,
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const char **parent_names, int num_parents,
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unsigned long flags, spinlock_t *lock);
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#endif /* __BERLIN2_DIV_H */
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