clk: sunxi-ng: div: Add mux table macros
Add some macros to ease the declaration of clocks that are using them. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
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@ -77,13 +77,16 @@ struct ccu_div {
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_shift, _width, _table, 0, \
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_shift, _width, _table, 0, \
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_flags)
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_flags)
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#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
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#define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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_parents, _table, \
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_reg, \
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_mshift, _mwidth, \
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_muxshift, _muxwidth, \
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_gate, _flags) \
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_gate, _flags) \
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struct ccu_div _struct = { \
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struct ccu_div _struct = { \
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.enable = _gate, \
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.enable = _gate, \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
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.mux = _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, _table), \
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.common = { \
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.common = { \
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.reg = _reg, \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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@ -93,11 +96,22 @@ struct ccu_div {
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}, \
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}, \
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}
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}
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#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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_gate, _flags) \
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SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
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_parents, NULL, \
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_reg, _mshift, _mwidth, \
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_muxshift, _muxwidth, \
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_gate, _flags)
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#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \
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#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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_flags) \
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_flags) \
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SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
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SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
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_mshift, _mwidth, _muxshift, _muxwidth, \
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_parents, NULL, \
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_reg, _mshift, _mwidth, \
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_muxshift, _muxwidth, \
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0, _flags)
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0, _flags)
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