[BNX2]: Refine tx coalescing setup.
Make the tx coalescing setup code independent of the MSIX vector. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -4438,18 +4438,21 @@ bnx2_init_chip(struct bnx2 *bp)
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}
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if (bp->flags & BNX2_FLAG_USING_MSIX) {
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u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
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BNX2_HC_SB_CONFIG_1;
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REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
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BNX2_HC_MSIX_BIT_VECTOR_VAL);
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REG_WR(bp, BNX2_HC_SB_CONFIG_1,
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REG_WR(bp, base,
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BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
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BNX2_HC_SB_CONFIG_1_ONE_SHOT);
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REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP_1,
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REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
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(bp->tx_quick_cons_trip_int << 16) |
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bp->tx_quick_cons_trip);
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REG_WR(bp, BNX2_HC_TX_TICKS_1,
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REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
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(bp->tx_ticks_int << 16) | bp->tx_ticks);
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val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
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@ -5510,6 +5510,15 @@ struct l2_fhdr {
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#define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0)
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#define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16)
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#define BNX2_HC_SB_CONFIG_SIZE (BNX2_HC_SB_CONFIG_2 - BNX2_HC_SB_CONFIG_1)
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#define BNX2_HC_COMP_PROD_TRIP_OFF (BNX2_HC_COMP_PROD_TRIP_1 - \
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BNX2_HC_SB_CONFIG_1)
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#define BNX2_HC_COM_TICKS_OFF (BNX2_HC_COM_TICKS_1 - BNX2_HC_SB_CONFIG_1)
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#define BNX2_HC_CMD_TICKS_OFF (BNX2_HC_CMD_TICKS_1 - BNX2_HC_SB_CONFIG_1)
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#define BNX2_HC_TX_QUICK_CONS_TRIP_OFF (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \
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BNX2_HC_SB_CONFIG_1)
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#define BNX2_HC_TX_TICKS_OFF (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
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/*
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* txp_reg definition
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