mlxsw: reg: Add Port Flow Control Configuration register
Add the Port Flow Control Configuration (PFCC) register, which configures both flow control and Priority-based Flow Control (PFC). Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2319,6 +2319,135 @@ static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
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mlxsw_reg_paos_e_set(payload, 1);
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}
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/* PFCC - Ports Flow Control Configuration Register
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* ------------------------------------------------
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* Configures and retrieves the per port flow control configuration.
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*/
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#define MLXSW_REG_PFCC_ID 0x5007
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#define MLXSW_REG_PFCC_LEN 0x20
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static const struct mlxsw_reg_info mlxsw_reg_pfcc = {
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.id = MLXSW_REG_PFCC_ID,
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.len = MLXSW_REG_PFCC_LEN,
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};
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/* reg_pfcc_local_port
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* Local port number.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
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/* reg_pfcc_pnat
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* Port number access type. Determines the way local_port is interpreted:
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* 0 - Local port number.
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* 1 - IB / label port number.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
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/* reg_pfcc_shl_cap
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* Send to higher layers capabilities:
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* 0 - No capability of sending Pause and PFC frames to higher layers.
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* 1 - Device has capability of sending Pause and PFC frames to higher
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* layers.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
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/* reg_pfcc_shl_opr
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* Send to higher layers operation:
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* 0 - Pause and PFC frames are handled by the port (default).
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* 1 - Pause and PFC frames are handled by the port and also sent to
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* higher layers. Only valid if shl_cap = 1.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
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/* reg_pfcc_ppan
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* Pause policy auto negotiation.
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* 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
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* 1 - Enabled. When auto-negotiation is performed, set the Pause policy
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* based on the auto-negotiation resolution.
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* Access: RW
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*
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* Note: The auto-negotiation advertisement is set according to pptx and
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* pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
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*/
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MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
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/* reg_pfcc_prio_mask_tx
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* Bit per priority indicating if Tx flow control policy should be
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* updated based on bit pfctx.
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* Access: WO
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*/
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MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
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/* reg_pfcc_prio_mask_rx
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* Bit per priority indicating if Rx flow control policy should be
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* updated based on bit pfcrx.
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* Access: WO
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*/
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MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
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/* reg_pfcc_pptx
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* Admin Pause policy on Tx.
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* 0 - Never generate Pause frames (default).
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* 1 - Generate Pause frames according to Rx buffer threshold.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
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/* reg_pfcc_aptx
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* Active (operational) Pause policy on Tx.
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* 0 - Never generate Pause frames.
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* 1 - Generate Pause frames according to Rx buffer threshold.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
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/* reg_pfcc_pfctx
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* Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
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* 0 - Never generate priority Pause frames on the specified priority
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* (default).
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* 1 - Generate priority Pause frames according to Rx buffer threshold on
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* the specified priority.
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* Access: RW
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*
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* Note: pfctx and pptx must be mutually exclusive.
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*/
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MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
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/* reg_pfcc_pprx
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* Admin Pause policy on Rx.
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* 0 - Ignore received Pause frames (default).
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* 1 - Respect received Pause frames.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
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/* reg_pfcc_aprx
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* Active (operational) Pause policy on Rx.
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* 0 - Ignore received Pause frames.
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* 1 - Respect received Pause frames.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
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/* reg_pfcc_pfcrx
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* Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
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* 0 - Ignore incoming priority Pause frames on the specified priority
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* (default).
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* 1 - Respect incoming priority Pause frames on the specified priority.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
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static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
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{
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MLXSW_REG_ZERO(pfcc, payload);
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mlxsw_reg_pfcc_local_port_set(payload, local_port);
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}
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/* PPCNT - Ports Performance Counters Register
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* -------------------------------------------
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* The PPCNT register retrieves per port performance counters.
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@ -3558,6 +3687,8 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
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return "PPAD";
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case MLXSW_REG_PAOS_ID:
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return "PAOS";
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case MLXSW_REG_PFCC_ID:
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return "PFCC";
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case MLXSW_REG_PPCNT_ID:
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return "PPCNT";
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case MLXSW_REG_PPTB_ID:
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