ARM: OMAP3: clock: remove clock3xxx.c file
This now only has a couple of variables within it, which are used outside the file itself. Move these variables to where they are actually used, and remove the file completely as it is now empty. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -186,7 +186,7 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o
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obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
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obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clock-common)
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obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
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obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
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obj-$(CONFIG_ARCH_OMAP3) += clock3517.o
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obj-$(CONFIG_ARCH_OMAP3) += clock3517.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
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@ -29,6 +29,8 @@
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#define CYCLES_PER_MHZ 1000000
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#define CYCLES_PER_MHZ 1000000
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struct clk *sdrc_ick_p, *arm_fck_p;
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/*
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/*
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* CORE DPLL (DPLL3) M2 divider rate programming functions
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* CORE DPLL (DPLL3) M2 divider rate programming functions
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*
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*
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@ -1,33 +0,0 @@
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/*
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* OMAP3-specific clock framework functions
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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*
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* Paul Walmsley
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* Jouni Högander
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "soc.h"
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#include "clock.h"
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#include "clock3xxx.h"
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#include "prm2xxx_3xxx.h"
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#include "prm-regbits-34xx.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-34xx.h"
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/* needed by omap3_core_dpll_m2_set_rate() */
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struct clk *sdrc_ick_p, *arm_fck_p;
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