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[Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg. 

Signed-off-by: Graf Yang <graf.yang@analog.com>
Cc: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Graf Yang 2008-04-24 04:43:14 +08:00 committed by Bryan Wu
parent db68254f06
commit 6ed8394230
8 changed files with 89 additions and 80 deletions
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16
arch/blackfin/kernel/bfin_gpio.c
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@ -95,14 +95,14 @@ enum {
AWA_data_clear = SYSCR, AWA_data_clear = SYSCR,
AWA_data_set = SYSCR, AWA_data_set = SYSCR,
AWA_toggle = SYSCR, AWA_toggle = SYSCR,
AWA_maska = UART_SCR, AWA_maska = BFIN_UART_SCR,
AWA_maska_clear = UART_SCR, AWA_maska_clear = BFIN_UART_SCR,
AWA_maska_set = UART_SCR, AWA_maska_set = BFIN_UART_SCR,
AWA_maska_toggle = UART_SCR, AWA_maska_toggle = BFIN_UART_SCR,
AWA_maskb = UART_GCTL, AWA_maskb = BFIN_UART_GCTL,
AWA_maskb_clear = UART_GCTL, AWA_maskb_clear = BFIN_UART_GCTL,
AWA_maskb_set = UART_GCTL, AWA_maskb_set = BFIN_UART_GCTL,
AWA_maskb_toggle = UART_GCTL, AWA_maskb_toggle = BFIN_UART_GCTL,
AWA_dir = SPORT1_STAT, AWA_dir = SPORT1_STAT,
AWA_polar = SPORT1_STAT, AWA_polar = SPORT1_STAT,
AWA_edge = SPORT1_STAT, AWA_edge = SPORT1_STAT,

16
arch/blackfin/mach-bf533/head.S
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@ -151,26 +151,26 @@ ENTRY(__start)
/* Initialise UART - when booting from u-boot, the UART is not disabled /* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */ * so if we dont initalize here, our serial console gets hosed */
p0.h = hi(UART_LCR); p0.h = hi(BFIN_UART_LCR);
p0.l = lo(UART_LCR); p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z); r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */ w[p0] = r0.L; /* To enable DLL writes */
ssync; ssync;
p0.h = hi(UART_DLL); p0.h = hi(BFIN_UART_DLL);
p0.l = lo(UART_DLL); p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z); r0 = 0x0(Z);
w[p0] = r0.L; w[p0] = r0.L;
ssync; ssync;
p0.h = hi(UART_DLH); p0.h = hi(BFIN_UART_DLH);
p0.l = lo(UART_DLH); p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z); r0 = 0x00(Z);
w[p0] = r0.L; w[p0] = r0.L;
ssync; ssync;
p0.h = hi(UART_GCTL); p0.h = hi(BFIN_UART_GCTL);
p0.l = lo(UART_GCTL); p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z); r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */ w[p0] = r0.L; /* To enable UART clock */
ssync; ssync;

16
arch/blackfin/mach-bf537/head.S
View File

@ -182,26 +182,26 @@ ENTRY(__start)
/* Initialise UART - when booting from u-boot, the UART is not disabled /* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */ * so if we dont initalize here, our serial console gets hosed */
p0.h = hi(UART_LCR); p0.h = hi(BFIN_UART_LCR);
p0.l = lo(UART_LCR); p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z); r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */ w[p0] = r0.L; /* To enable DLL writes */
ssync; ssync;
p0.h = hi(UART_DLL); p0.h = hi(BFIN_UART_DLL);
p0.l = lo(UART_DLL); p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z); r0 = 0x0(Z);
w[p0] = r0.L; w[p0] = r0.L;
ssync; ssync;
p0.h = hi(UART_DLH); p0.h = hi(BFIN_UART_DLH);
p0.l = lo(UART_DLH); p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z); r0 = 0x00(Z);
w[p0] = r0.L; w[p0] = r0.L;
ssync; ssync;
p0.h = hi(UART_GCTL); p0.h = hi(BFIN_UART_GCTL);
p0.l = lo(UART_GCTL); p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z); r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */ w[p0] = r0.L; /* To enable UART clock */
ssync; ssync;

16
arch/blackfin/mach-bf561/head.S
View File

@ -139,26 +139,26 @@ ENTRY(__start)
/* Initialise UART - when booting from u-boot, the UART is not disabled /* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */ * so if we dont initalize here, our serial console gets hosed */
p0.h = hi(UART_LCR); p0.h = hi(BFIN_UART_LCR);
p0.l = lo(UART_LCR); p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z); r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */ w[p0] = r0.L; /* To enable DLL writes */
ssync; ssync;
p0.h = hi(UART_DLL); p0.h = hi(BFIN_UART_DLL);
p0.l = lo(UART_DLL); p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z); r0 = 0x0(Z);
w[p0] = r0.L; w[p0] = r0.L;
ssync; ssync;
p0.h = hi(UART_DLH); p0.h = hi(BFIN_UART_DLH);
p0.l = lo(UART_DLH); p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z); r0 = 0x00(Z);
w[p0] = r0.L; w[p0] = r0.L;
ssync; ssync;
p0.h = hi(UART_GCTL); p0.h = hi(BFIN_UART_GCTL);
p0.l = lo(UART_GCTL); p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z); r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */ w[p0] = r0.L; /* To enable UART clock */
ssync; ssync;

29
include/asm-blackfin/mach-bf533/defBF532.h
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@ -88,20 +88,25 @@
#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
/* UART Controller (0xFFC00400 - 0xFFC004FF) */ /* UART Controller (0xFFC00400 - 0xFFC004FF) */
#define UART_THR 0xFFC00400 /* Transmit Holding register */
#define UART_RBR 0xFFC00400 /* Receive Buffer register */ /*
#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ * Because include/linux/serial_reg.h have defined UART_*,
#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ * So we define blackfin uart regs to BFIN_UART_*.
#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ */
#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ #define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
#define UART_LCR 0xFFC0040C /* Line Control Register */ #define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
#define UART_MCR 0xFFC00410 /* Modem Control Register */ #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
#define UART_LSR 0xFFC00414 /* Line Status Register */ #define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
#if 0 #if 0
#define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ #define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
#endif #endif
#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ #define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
#define UART_GCTL 0xFFC00424 /* Global Control Register */ #define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI0_REGBASE 0xFFC00500 #define SPI0_REGBASE 0xFFC00500

24
include/asm-blackfin/mach-bf537/blackfin.h
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@ -82,8 +82,6 @@
#define STATUS_P1 0x02 #define STATUS_P1 0x02
#define STATUS_P0 0x01 #define STATUS_P0 0x01
/* UART 0*/
/* DMA Channnel */ /* DMA Channnel */
#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
@ -106,37 +104,37 @@
/* MMR Registers*/ /* MMR Registers*/
#define bfin_read_UART_THR() bfin_read_UART0_THR() #define bfin_read_UART_THR() bfin_read_UART0_THR()
#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) #define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
#define UART_THR UART0_THR #define BFIN_UART_THR UART0_THR
#define bfin_read_UART_RBR() bfin_read_UART0_RBR() #define bfin_read_UART_RBR() bfin_read_UART0_RBR()
#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) #define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
#define UART_RBR UART0_RBR #define BFIN_UART_RBR UART0_RBR
#define bfin_read_UART_DLL() bfin_read_UART0_DLL() #define bfin_read_UART_DLL() bfin_read_UART0_DLL()
#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) #define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
#define UART_DLL UART0_DLL #define BFIN_UART_DLL UART0_DLL
#define bfin_read_UART_IER() bfin_read_UART0_IER() #define bfin_read_UART_IER() bfin_read_UART0_IER()
#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) #define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
#define UART_IER UART0_IER #define BFIN_UART_IER UART0_IER
#define bfin_read_UART_DLH() bfin_read_UART0_DLH() #define bfin_read_UART_DLH() bfin_read_UART0_DLH()
#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) #define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
#define UART_DLH UART0_DLH #define BFIN_UART_DLH UART0_DLH
#define bfin_read_UART_IIR() bfin_read_UART0_IIR() #define bfin_read_UART_IIR() bfin_read_UART0_IIR()
#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) #define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
#define UART_IIR UART0_IIR #define BFIN_UART_IIR UART0_IIR
#define bfin_read_UART_LCR() bfin_read_UART0_LCR() #define bfin_read_UART_LCR() bfin_read_UART0_LCR()
#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) #define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
#define UART_LCR UART0_LCR #define BFIN_UART_LCR UART0_LCR
#define bfin_read_UART_MCR() bfin_read_UART0_MCR() #define bfin_read_UART_MCR() bfin_read_UART0_MCR()
#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) #define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
#define UART_MCR UART0_MCR #define BFIN_UART_MCR UART0_MCR
#define bfin_read_UART_LSR() bfin_read_UART0_LSR() #define bfin_read_UART_LSR() bfin_read_UART0_LSR()
#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) #define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
#define UART_LSR UART0_LSR #define BFIN_UART_LSR UART0_LSR
#define bfin_read_UART_SCR() bfin_read_UART0_SCR() #define bfin_read_UART_SCR() bfin_read_UART0_SCR()
#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) #define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
#define UART_SCR UART0_SCR #define BFIN_UART_SCR UART0_SCR
#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() #define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
#define UART_GCTL UART0_GCTL #define BFIN_UART_GCTL UART0_GCTL
/* DPMC*/ /* DPMC*/
#define bfin_read_STOPCK_OFF() bfin_read_STOPCK() #define bfin_read_STOPCK_OFF() bfin_read_STOPCK()

23
include/asm-blackfin/mach-bf548/blackfin.h
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@ -153,17 +153,18 @@
#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) #define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() #define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) #define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
#define UART_THR UART1_THR
#define UART_RBR UART1_RBR #define BFIN_UART_THR UART1_THR
#define UART_DLL UART1_DLL #define BFIN_UART_RBR UART1_RBR
#define UART_IER UART1_IER #define BFIN_UART_DLL UART1_DLL
#define UART_DLH UART1_DLH #define BFIN_UART_IER UART1_IER
#define UART_IIR UART1_IIR #define BFIN_UART_DLH UART1_DLH
#define UART_LCR UART1_LCR #define BFIN_UART_IIR UART1_IIR
#define UART_MCR UART1_MCR #define BFIN_UART_LCR UART1_LCR
#define UART_LSR UART1_LSR #define BFIN_UART_MCR UART1_MCR
#define UART_SCR UART1_SCR #define BFIN_UART_LSR UART1_LSR
#define UART_GCTL UART1_GCTL #define BFIN_UART_SCR UART1_SCR
#define BFIN_UART_GCTL UART1_GCTL
/* PLL_DIV Masks */ /* PLL_DIV Masks */
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */

29
include/asm-blackfin/mach-bf561/defBF561.h
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@ -110,18 +110,23 @@
#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */ #define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
/* UART Controller (0xFFC00400 - 0xFFC004FF) */ /* UART Controller (0xFFC00400 - 0xFFC004FF) */
#define UART_THR 0xFFC00400 /* Transmit Holding register */
#define UART_RBR 0xFFC00400 /* Receive Buffer register */ /*
#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ * Because include/linux/serial_reg.h have defined UART_*,
#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ * So we define blackfin uart regs to BFIN_UART0_*.
#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ */
#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ #define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
#define UART_LCR 0xFFC0040C /* Line Control Register */ #define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
#define UART_MCR 0xFFC00410 /* Modem Control Register */ #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
#define UART_LSR 0xFFC00414 /* Line Status Register */ #define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
#define UART_MSR 0xFFC00418 /* Modem Status Register */ #define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ #define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
#define UART_GCTL 0xFFC00424 /* Global Control Register */ #define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI0_REGBASE 0xFFC00500 #define SPI0_REGBASE 0xFFC00500