Samsung cleanup 2nd for v3.14
- remove <mach/regs-clock.h> for exynos - remove <mach/regs-irq.h> for exynos - local <mach/regs-pmu.h> into mach-exynos - select PM_GENERIC_DOMAINS for ARCH_EXYNOS4 instead of each SOC_EXYNOS4XXX in Kconfig - call pm_genpd_poweroff_unused() instead of via exynos_pm_late_initcall() because no need to handle whether CONFIG_PM_GENERIC_DOMAINS is enalbed -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJStdAiAAoJEA0Cl+kVi2xqNQ4P/j+t1mbZWnn8n5iwDyEkS0cQ xYH97eewSFFgbiO54eFCNM1xQoAyJhASxPuxi8wIVvYriOjgZ+IGsWXQqyGf0un9 Zui4v6dinuoQFqxhMsy10qSm4BH5URNlf8ApFFPdhReO3zNTD0SWzou3PAsFSoE4 DMCboHQ6z7ku+tELjN56fQHcDRmUx4MpHc4Mj57ESr4LXMHbajTQhfq1M+F//SWh wnsuD1lFDDS2MnpRclhVajT7Rogl7CXVpXB8FYN6/ZxdwraJbPh3qpubsYVJpcwQ Z0h0dXXPplw2HQRcruhSO5POEK16Q5TtFRw2YlUdN+Zd9rljwwlc5tBDl6UMi+RQ 6p82BMl+LGpt2tAI3R1Tgj/V9BX5ijmLpXQAG9dLi/6CQAEKEGJJhsUWZV8DIo6g 4BARQNR+I13izvI1MYLg4QS2Yx2H5jvR1ewPyMuSH6DuK7ZrHICQhSbslyqfAKH4 xGie6HVPAm+t0dhUrwppcDDI9TWE4TFeiilV+Tl8nLHAnSBdZvDSMKW94nYxzlsb uQJZHXMI+OgzgND4HCyE7vc7PCwvkF1YPtmt6/zkH4D++gk64LIxojyVAiEm8bAJ 7a2vCnIjOLaaC3/s5hN2dZQG6IeXX70eqG0NE1cHqwTxlj5dCxmNds1nHUgBiyHq FJ/S/ns7cGNkOgbHB9LV =NgIt -----END PGP SIGNATURE----- Merge tag 'samsung-cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup From Kukjin Kim: Samsung cleanup 2nd for v3.14 - remove <mach/regs-clock.h> for exynos - remove <mach/regs-irq.h> for exynos - local <mach/regs-pmu.h> into mach-exynos - select PM_GENERIC_DOMAINS for ARCH_EXYNOS4 instead of each SOC_EXYNOS4XXX in Kconfig - call pm_genpd_poweroff_unused() instead of via exynos_pm_late_initcall() because no need to handle whether CONFIG_PM_GENERIC_DOMAINS is enalbed * tag 'samsung-cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Kill exynos_pm_late_initcall() ARM: EXYNOS: Consolidate selection of PM_GENERIC_DOMAINS for Exynos4 PM / devfreq: use inclusion <mach/map.h> instead of <plat/map-s5p.h> ARM: EXYNOS: remove <mach/regs-clock.h> for exynos ARM: EXYNOS: local definitions for cpuidle.c into mach-exynos dir cpufreq: exynos: move definitions for exynos-cpufreq into drivers/cpufreq/ ARM: EXYNOS: local definitions for pm.c into mach-exynos dir PM / devfreq: move definitions for exynos4_bus into drivers/devfreq ARM: EXYNOS: cleanup <mach/regs-clock.h> ARM: EXYNOS: cleanup <mach/regs-irq.h> ARM: EXYNOS: local regs-pmu.h header file ARM: EXYNOS: remove inclusion <mach/regs-pmu.h> into another headers ARM: EXYNOS: cleanup <mach/regs-pmu.h> Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
6eb5c9db7a
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@ -24,6 +24,7 @@ config ARCH_EXYNOS4
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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select PINCTRL
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select PM_GENERIC_DOMAINS if PM
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select S5P_DEV_MFC
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help
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Samsung EXYNOS4 SoCs based systems
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@ -48,7 +49,6 @@ config CPU_EXYNOS4210
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select ARCH_HAS_BANDGAP
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select ARM_CPU_SUSPEND if PM
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select PINCTRL_EXYNOS
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select PM_GENERIC_DOMAINS if PM
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select S5P_PM if PM
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select S5P_SLEEP if PM
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select SAMSUNG_DMADEV
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@ -61,7 +61,6 @@ config SOC_EXYNOS4212
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depends on ARCH_EXYNOS4
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select ARCH_HAS_BANDGAP
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select PINCTRL_EXYNOS
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select PM_GENERIC_DOMAINS if PM
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select S5P_PM if PM
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select S5P_SLEEP if PM
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select SAMSUNG_DMADEV
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@ -74,7 +73,6 @@ config SOC_EXYNOS4412
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depends on ARCH_EXYNOS4
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select ARCH_HAS_BANDGAP
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select PINCTRL_EXYNOS
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select PM_GENERIC_DOMAINS if PM
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select SAMSUNG_DMADEV
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help
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Enable EXYNOS4412 SoC support
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@ -23,6 +23,7 @@
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <linux/of_irq.h>
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#include <linux/pm_domain.h>
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#include <linux/export.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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@ -37,14 +38,13 @@
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#include <asm/mach/irq.h>
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#include <asm/cacheflush.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-pmu.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/regs-serial.h>
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#include "common.h"
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#include "regs-pmu.h"
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#define L2_AUX_VAL 0x7C470001
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#define L2_AUX_MASK 0xC200ffff
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@ -309,7 +309,7 @@ void __init exynos_init_late(void)
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/* to be supported later */
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return;
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exynos_pm_late_initcall();
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pm_genpd_poweroff_unused();
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}
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static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
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@ -26,12 +26,6 @@ void exynos_init_late(void);
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void exynos_firmware_init(void);
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#ifdef CONFIG_PM_GENERIC_DOMAINS
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int exynos_pm_late_initcall(void);
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#else
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static inline int exynos_pm_late_initcall(void) { return 0; }
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#endif
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extern struct smp_operations exynos_smp_ops;
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extern void exynos_cpu_die(unsigned int cpu);
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@ -22,13 +22,15 @@
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#include <asm/suspend.h>
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#include <asm/unified.h>
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#include <asm/cpuidle.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-pmu.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <mach/pm-core.h>
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#include <mach/map.h>
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#include "common.h"
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#include "regs-pmu.h"
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#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
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S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
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@ -39,6 +41,25 @@
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#define S5P_CHECK_AFTR 0xFCBA0D10
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#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020)
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#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024)
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#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
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#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
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#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
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#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
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#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
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#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
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#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
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#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
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#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
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#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
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#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
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#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
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#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
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#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
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static int exynos4_enter_lowpower(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index);
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@ -19,10 +19,10 @@
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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#include <mach/regs-pmu.h>
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#include <plat/cpu.h>
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#include "common.h"
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#include "regs-pmu.h"
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static inline void cpu_enter_lowpower_a9(void)
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{
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@ -19,7 +19,10 @@
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#define __ASM_ARCH_PM_CORE_H __FILE__
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#include <linux/of.h>
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#include <mach/regs-pmu.h>
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#include <mach/map.h>
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#define S5P_EINT_WAKEUP_MASK (S5P_VA_PMU + 0x0604)
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#define S5P_WAKEUP_MASK (S5P_VA_PMU + 0x0608)
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#ifdef CONFIG_PINCTRL_EXYNOS
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extern u32 exynos_get_eint_wake_mask(void);
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@ -1,372 +0,0 @@
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/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4 - Clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_CLOCK_H
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#define __ASM_ARCH_REGS_CLOCK_H __FILE__
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#include <plat/cpu.h>
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#include <mach/map.h>
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#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
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#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
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#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
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#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
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#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
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#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
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#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)
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#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
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#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
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#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
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#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
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#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
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#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
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#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)
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#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)
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#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)
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#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)
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#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)
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#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)
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#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)
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#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)
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#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)
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#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)
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#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)
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#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)
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#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
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#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
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#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
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#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
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#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
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#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
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#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
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#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
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#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
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#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
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#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)
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#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
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#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)
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#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)
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#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)
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#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)
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#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)
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#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)
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#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)
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#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)
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#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)
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#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)
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#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)
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#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)
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#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)
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#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)
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#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)
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#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
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#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
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#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
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#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
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#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)
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#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)
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#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)
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#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
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EXYNOS_CLKREG(0x0C930) : \
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EXYNOS_CLKREG(0x04930))
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#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
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#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
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#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)
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#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)
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#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)
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#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)
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#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
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EXYNOS_CLKREG(0x0C960) : \
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EXYNOS_CLKREG(0x08960))
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#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)
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#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)
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#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)
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#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
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#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)
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#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
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#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
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#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
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#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
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#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)
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#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
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#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
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#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
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#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
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EXYNOS_CLKREG(0x14004) : \
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EXYNOS_CLKREG(0x10008))
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#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)
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#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)
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#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \
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EXYNOS_CLKREG(0x14108) : \
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EXYNOS_CLKREG(0x10108))
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#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \
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EXYNOS_CLKREG(0x1410C) : \
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EXYNOS_CLKREG(0x1010C))
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#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
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#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
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#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)
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#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)
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#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
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#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
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#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
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#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
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#define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800)
|
||||
#define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804)
|
||||
|
||||
#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
|
||||
|
||||
#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
|
||||
#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)
|
||||
#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
|
||||
#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
|
||||
|
||||
#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)
|
||||
#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
|
||||
|
||||
#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)
|
||||
#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
|
||||
|
||||
#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
|
||||
#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)
|
||||
#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
|
||||
#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
|
||||
#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28
|
||||
#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0
|
||||
#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4
|
||||
#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8
|
||||
#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
|
||||
#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
|
||||
#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
|
||||
#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
|
||||
#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
|
||||
#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
|
||||
#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
|
||||
|
||||
/* Only for EXYNOS4210 */
|
||||
|
||||
#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
|
||||
#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
|
||||
#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
|
||||
#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)
|
||||
|
||||
/* Only for EXYNOS4212 */
|
||||
|
||||
#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
|
||||
|
||||
#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
|
||||
|
||||
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
|
||||
|
||||
/* For EXYNOS5250 */
|
||||
|
||||
#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
|
||||
#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
|
||||
#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
|
||||
#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
|
||||
#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
|
||||
#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
|
||||
#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
|
||||
#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
|
||||
|
||||
#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
|
||||
#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
|
||||
|
||||
#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
|
||||
#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
|
||||
|
||||
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
|
||||
|
||||
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
|
||||
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
|
||||
#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
|
||||
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
|
||||
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
|
||||
#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
|
||||
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
|
||||
|
||||
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
|
||||
#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
|
||||
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
|
||||
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
|
||||
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
|
||||
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
|
||||
#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
|
||||
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
|
||||
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
|
||||
#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
|
||||
#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
|
||||
|
||||
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
|
||||
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
|
||||
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
|
||||
#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
|
||||
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
|
||||
|
||||
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
|
||||
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
|
||||
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
|
||||
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
|
||||
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
|
||||
#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
|
||||
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
|
||||
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
|
||||
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
|
||||
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
|
||||
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
|
||||
#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
|
||||
#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
|
||||
#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
|
||||
#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
|
||||
#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
|
||||
#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
|
||||
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
|
||||
#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
|
||||
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
|
||||
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
|
||||
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
|
||||
#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
|
||||
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
|
||||
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
|
||||
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
|
||||
#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
|
||||
#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
|
||||
#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
|
||||
|
||||
#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
|
||||
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
|
||||
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
|
||||
|
||||
#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
|
||||
|
||||
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
|
||||
|
||||
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
|
||||
|
||||
#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
|
||||
#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
|
||||
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
|
||||
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
|
||||
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
|
||||
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
|
||||
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
|
||||
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
|
||||
|
||||
#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
|
||||
#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
|
||||
#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
|
||||
#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
|
||||
#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
|
||||
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
|
||||
|
||||
/* Compatibility defines and inclusion */
|
||||
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
#define S5P_EPLL_CON EXYNOS4_EPLL_CON0
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_CLOCK_H */
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - IRQ register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_IRQ_H
|
||||
#define __ASM_ARCH_REGS_IRQ_H __FILE__
|
||||
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_IRQ_H */
|
||||
|
|
@ -14,10 +14,10 @@
|
|||
#include <linux/io.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
#include <plat/mfc.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "regs-pmu.h"
|
||||
|
||||
static void __init exynos5_dt_machine_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -27,12 +27,11 @@
|
|||
#include <asm/firmware.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "regs-pmu.h"
|
||||
|
||||
extern void exynos4_secondary_startup(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -29,12 +29,35 @@
|
|||
#include <plat/pll.h>
|
||||
#include <plat/regs-srom.h>
|
||||
|
||||
#include <mach/regs-irq.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/pm-core.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "regs-pmu.h"
|
||||
|
||||
#define EXYNOS4_EPLL_LOCK (S5P_VA_CMU + 0x0C010)
|
||||
#define EXYNOS4_VPLL_LOCK (S5P_VA_CMU + 0x0C020)
|
||||
|
||||
#define EXYNOS4_EPLL_CON0 (S5P_VA_CMU + 0x0C110)
|
||||
#define EXYNOS4_EPLL_CON1 (S5P_VA_CMU + 0x0C114)
|
||||
#define EXYNOS4_VPLL_CON0 (S5P_VA_CMU + 0x0C120)
|
||||
#define EXYNOS4_VPLL_CON1 (S5P_VA_CMU + 0x0C124)
|
||||
|
||||
#define EXYNOS4_CLKSRC_MASK_TOP (S5P_VA_CMU + 0x0C310)
|
||||
#define EXYNOS4_CLKSRC_MASK_CAM (S5P_VA_CMU + 0x0C320)
|
||||
#define EXYNOS4_CLKSRC_MASK_TV (S5P_VA_CMU + 0x0C324)
|
||||
#define EXYNOS4_CLKSRC_MASK_LCD0 (S5P_VA_CMU + 0x0C334)
|
||||
#define EXYNOS4_CLKSRC_MASK_MAUDIO (S5P_VA_CMU + 0x0C33C)
|
||||
#define EXYNOS4_CLKSRC_MASK_FSYS (S5P_VA_CMU + 0x0C340)
|
||||
#define EXYNOS4_CLKSRC_MASK_PERIL0 (S5P_VA_CMU + 0x0C350)
|
||||
#define EXYNOS4_CLKSRC_MASK_PERIL1 (S5P_VA_CMU + 0x0C354)
|
||||
|
||||
#define EXYNOS4_CLKSRC_MASK_DMC (S5P_VA_CMU + 0x10300)
|
||||
|
||||
#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
|
||||
#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
|
||||
|
||||
#define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338)
|
||||
|
||||
static const struct sleep_save exynos4_set_clksrc[] = {
|
||||
{ .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
|
||||
|
|
|
|||
|
|
@ -22,9 +22,10 @@
|
|||
#include <linux/of_platform.h>
|
||||
#include <linux/sched.h>
|
||||
|
||||
#include <mach/regs-pmu.h>
|
||||
#include <plat/devs.h>
|
||||
|
||||
#include "regs-pmu.h"
|
||||
|
||||
/*
|
||||
* Exynos specific wrapper around the generic power domain
|
||||
*/
|
||||
|
|
@ -183,9 +184,3 @@ static __init int exynos4_pm_init_power_domain(void)
|
|||
return 0;
|
||||
}
|
||||
arch_initcall(exynos4_pm_init_power_domain);
|
||||
|
||||
int __init exynos_pm_late_initcall(void)
|
||||
{
|
||||
pm_genpd_poweroff_unused();
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,9 +13,10 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/bug.h>
|
||||
|
||||
#include <mach/regs-clock.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "regs-pmu.h"
|
||||
|
||||
static const struct exynos_pmu_conf *exynos_pmu_config;
|
||||
|
||||
|
|
|
|||
|
|
@ -24,31 +24,16 @@
|
|||
#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
|
||||
|
||||
#define S5P_USE_STANDBY_WFI0 (1 << 16)
|
||||
#define S5P_USE_STANDBY_WFI1 (1 << 17)
|
||||
#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18)
|
||||
#define S5P_USE_STANDBY_WFE0 (1 << 24)
|
||||
#define S5P_USE_STANDBY_WFE1 (1 << 25)
|
||||
#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
|
||||
|
||||
#define S5P_SWRESET S5P_PMUREG(0x0400)
|
||||
#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
|
||||
#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
|
||||
|
||||
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
|
||||
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
|
||||
#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
|
||||
|
||||
#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
|
||||
#define S5P_HDMI_PHY_ENABLE (1 << 0)
|
||||
|
||||
#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
|
||||
#define S5P_DAC_PHY_ENABLE (1 << 0)
|
||||
|
||||
#define S5P_INFORM0 S5P_PMUREG(0x0800)
|
||||
#define S5P_INFORM1 S5P_PMUREG(0x0804)
|
||||
#define S5P_INFORM2 S5P_PMUREG(0x0808)
|
||||
#define S5P_INFORM3 S5P_PMUREG(0x080C)
|
||||
#define S5P_INFORM4 S5P_PMUREG(0x0810)
|
||||
#define S5P_INFORM5 S5P_PMUREG(0x0814)
|
||||
#define S5P_INFORM6 S5P_PMUREG(0x0818)
|
||||
#define S5P_INFORM7 S5P_PMUREG(0x081C)
|
||||
|
|
@ -119,23 +104,8 @@
|
|||
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
|
||||
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
|
||||
|
||||
#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
|
||||
#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
|
||||
#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
|
||||
#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
|
||||
#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
|
||||
|
||||
#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
|
||||
#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
|
||||
#define S5P_CAM_OPTION S5P_PMUREG(0x3C08)
|
||||
#define S5P_TV_OPTION S5P_PMUREG(0x3C28)
|
||||
#define S5P_MFC_OPTION S5P_PMUREG(0x3C48)
|
||||
#define S5P_G3D_OPTION S5P_PMUREG(0x3C68)
|
||||
#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88)
|
||||
#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8)
|
||||
#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8)
|
||||
#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8)
|
||||
#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08)
|
||||
|
||||
#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
|
||||
#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
|
||||
|
|
@ -145,28 +115,12 @@
|
|||
#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
|
||||
#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
|
||||
|
||||
#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
|
||||
#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
|
||||
#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
|
||||
#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
|
||||
#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
|
||||
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
|
||||
|
||||
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
|
||||
#define S5P_CORE_LOCAL_PWR_EN 0x3
|
||||
#define S5P_INT_LOCAL_PWR_EN 0x7
|
||||
|
||||
#define S5P_CHECK_SLEEP 0x00000BAD
|
||||
|
||||
/* Only for EXYNOS4210 */
|
||||
#define S5P_USBDEVICE_PHY_CONTROL S5P_PMUREG(0x0704)
|
||||
#define S5P_USBDEVICE_PHY_ENABLE (1 << 0)
|
||||
|
||||
#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
|
||||
#define S5P_USBHOST_PHY_ENABLE (1 << 0)
|
||||
|
||||
#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
|
||||
|
||||
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
|
||||
#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
|
||||
#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
|
||||
|
|
@ -174,8 +128,6 @@
|
|||
#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
|
||||
#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
|
||||
|
||||
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
|
||||
|
||||
/* Only for EXYNOS4x12 */
|
||||
#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
|
||||
#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
|
||||
|
|
@ -343,13 +295,9 @@
|
|||
#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
|
||||
#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
|
||||
#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
|
||||
#define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004)
|
||||
#define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024)
|
||||
#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
|
||||
#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
|
||||
#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
|
||||
#define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060)
|
||||
#define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064)
|
||||
#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
|
||||
#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
|
||||
#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
|
||||
|
|
@ -357,7 +305,6 @@
|
|||
#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
|
||||
#define EXYNOS5_USE_SC_COUNTER (1 << 0)
|
||||
|
||||
#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2)
|
||||
#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
|
||||
|
||||
#define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24)
|
||||
|
|
@ -28,8 +28,10 @@
|
|||
#ifdef CONFIG_SAMSUNG_ATAGS
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#ifndef CONFIG_ARCH_EXYNOS
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/regs-irq.h>
|
||||
#endif
|
||||
#include <mach/irqs.h>
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,10 @@
|
|||
#include <mach/map.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#ifndef CONFIG_ARCH_EXYNOS
|
||||
#include <mach/regs-irq.h>
|
||||
#endif
|
||||
|
||||
/* state for IRQs over sleep */
|
||||
|
||||
|
|
|
|||
|
|
@ -67,3 +67,25 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
|
|||
return -EOPNOTSUPP;
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU + 0x14200)
|
||||
#define EXYNOS4_CLKMUX_STATCPU (S5P_VA_CMU + 0x14400)
|
||||
|
||||
#define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU + 0x14500)
|
||||
#define EXYNOS4_CLKDIV_CPU1 (S5P_VA_CMU + 0x14504)
|
||||
#define EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600)
|
||||
#define EXYNOS4_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x14604)
|
||||
|
||||
#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
|
||||
#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
|
||||
|
||||
#define EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x00000)
|
||||
#define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100)
|
||||
#define EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400)
|
||||
#define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU + 0x00500)
|
||||
#define EXYNOS5_CLKDIV_CPU1 (S5P_VA_CMU + 0x00504)
|
||||
#define EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU + 0x00600)
|
||||
#define EXYNOS5_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x00604)
|
||||
|
|
|
|||
|
|
@ -17,8 +17,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/cpufreq.h>
|
||||
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "exynos-cpufreq.h"
|
||||
|
||||
static struct clk *cpu_clk;
|
||||
|
|
|
|||
|
|
@ -17,8 +17,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/cpufreq.h>
|
||||
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "exynos-cpufreq.h"
|
||||
|
||||
static struct clk *cpu_clk;
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
#include <linux/cpufreq.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
#include "exynos-cpufreq.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -30,9 +30,9 @@
|
|||
extern unsigned int exynos_result_of_asv;
|
||||
#endif
|
||||
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/map-s5p.h>
|
||||
#include "exynos4_bus.h"
|
||||
|
||||
#define MAX_SAFEVOLT 1200000 /* 1.2V */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS4 BUS header
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __DEVFREQ_EXYNOS4_BUS_H
|
||||
#define __DEVFREQ_EXYNOS4_BUS_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define EXYNOS4_CLKDIV_LEFTBUS (S5P_VA_CMU + 0x04500)
|
||||
#define EXYNOS4_CLKDIV_STAT_LEFTBUS (S5P_VA_CMU + 0x04600)
|
||||
|
||||
#define EXYNOS4_CLKDIV_RIGHTBUS (S5P_VA_CMU + 0x08500)
|
||||
#define EXYNOS4_CLKDIV_STAT_RIGHTBUS (S5P_VA_CMU + 0x08600)
|
||||
|
||||
#define EXYNOS4_CLKDIV_TOP (S5P_VA_CMU + 0x0C510)
|
||||
#define EXYNOS4_CLKDIV_CAM (S5P_VA_CMU + 0x0C520)
|
||||
#define EXYNOS4_CLKDIV_MFC (S5P_VA_CMU + 0x0C528)
|
||||
|
||||
#define EXYNOS4_CLKDIV_STAT_TOP (S5P_VA_CMU + 0x0C610)
|
||||
#define EXYNOS4_CLKDIV_STAT_MFC (S5P_VA_CMU + 0x0C628)
|
||||
|
||||
#define EXYNOS4210_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x0C930)
|
||||
#define EXYNOS4212_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x04930)
|
||||
|
||||
#define EXYNOS4_CLKDIV_DMC0 (S5P_VA_CMU + 0x10500)
|
||||
#define EXYNOS4_CLKDIV_DMC1 (S5P_VA_CMU + 0x10504)
|
||||
#define EXYNOS4_CLKDIV_STAT_DMC0 (S5P_VA_CMU + 0x10600)
|
||||
#define EXYNOS4_CLKDIV_STAT_DMC1 (S5P_VA_CMU + 0x10604)
|
||||
|
||||
#define EXYNOS4_DMC_PAUSE_CTRL (S5P_VA_CMU + 0x11094)
|
||||
#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
|
||||
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
|
||||
#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
|
||||
#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
|
||||
#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
|
||||
|
||||
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
|
||||
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
|
||||
#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
|
||||
#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
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#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
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#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
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#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
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#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
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#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
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#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
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#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
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#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
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#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
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#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
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#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
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#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
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#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
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#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
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#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
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#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
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#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
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#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
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#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
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#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
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#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
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#define EXYNOS4_CLKDIV_CAM1 (S5P_VA_CMU + 0x0C568)
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#define EXYNOS4_CLKDIV_STAT_CAM1 (S5P_VA_CMU + 0x0C668)
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#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
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#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
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#endif /* __DEVFREQ_EXYNOS4_BUS_H */
|
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Loading…
Reference in New Issue