amdkfd: Add mqd_manager module
The mqd_manager module handles MQD data structures. MQD stands for Memory Queue Descriptor, which is used by the H/W to keep the usermode queue state in memory. v3: Removed new typedefs Removed pragma pack 4 Remove cik_mqds.h file Changed lower_32/upper_32 calls to use linux macros Used new gart allocation functions Added documentation v4: Added missing initialization of the addr field in init_mqd() Setting the hqd persistent.preload_req bit ON so that when queues switches on/off, their context will kept and read from the mqd when the cp reassign them, and thus the dispatched workload context kept consistent without any interrupts. v5: Move amdkfd from drm/radeon/ to drm/amd/ Change format of mqd structure to match latest KV firmware Add support for AQL queues creation to enable working with open-source HSA runtime. Various fixes Signed-off-by: Ben Goz <ben.goz@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
This commit is contained in:
Ben Goz
Oded Gabbay
parent
ed8aab4594
commit
6e99df5741
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@ -6,6 +6,6 @@ ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/
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amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \
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kfd_pasid.o kfd_doorbell.o kfd_flat_memory.o \
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kfd_process.o kfd_queue.o
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kfd_process.o kfd_queue.o kfd_mqd_manager.o
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obj-$(CONFIG_HSA_AMD) += amdkfd.o
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@ -0,0 +1,221 @@
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef CIK_REGS_H
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#define CIK_REGS_H
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#define IH_VMID_0_LUT 0x3D40u
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#define BIF_DOORBELL_CNTL 0x530Cu
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#define SRBM_GFX_CNTL 0xE44
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#define PIPEID(x) ((x) << 0)
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#define MEID(x) ((x) << 2)
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#define VMID(x) ((x) << 4)
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#define QUEUEID(x) ((x) << 8)
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#define SQ_CONFIG 0x8C00
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#define SH_MEM_BASES 0x8C28
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/* if PTR32, these are the bases for scratch and lds */
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#define PRIVATE_BASE(x) ((x) << 0) /* scratch */
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#define SHARED_BASE(x) ((x) << 16) /* LDS */
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#define SH_MEM_APE1_BASE 0x8C2C
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/* if PTR32, this is the base location of GPUVM */
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#define SH_MEM_APE1_LIMIT 0x8C30
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/* if PTR32, this is the upper limit of GPUVM */
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#define SH_MEM_CONFIG 0x8C34
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#define PTR32 (1 << 0)
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#define PRIVATE_ATC (1 << 1)
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#define ALIGNMENT_MODE(x) ((x) << 2)
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#define SH_MEM_ALIGNMENT_MODE_DWORD 0
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#define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
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#define SH_MEM_ALIGNMENT_MODE_STRICT 2
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#define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3
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#define DEFAULT_MTYPE(x) ((x) << 4)
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#define APE1_MTYPE(x) ((x) << 7)
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/* valid for both DEFAULT_MTYPE and APE1_MTYPE */
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#define MTYPE_CACHED 0
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#define MTYPE_NONCACHED 3
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#define SH_STATIC_MEM_CONFIG 0x9604u
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#define TC_CFG_L1_LOAD_POLICY0 0xAC68
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#define TC_CFG_L1_LOAD_POLICY1 0xAC6C
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#define TC_CFG_L1_STORE_POLICY 0xAC70
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#define TC_CFG_L2_LOAD_POLICY0 0xAC74
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#define TC_CFG_L2_LOAD_POLICY1 0xAC78
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#define TC_CFG_L2_STORE_POLICY0 0xAC7C
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#define TC_CFG_L2_STORE_POLICY1 0xAC80
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#define TC_CFG_L2_ATOMIC_POLICY 0xAC84
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#define TC_CFG_L1_VOLATILE 0xAC88
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#define TC_CFG_L2_VOLATILE 0xAC8C
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#define CP_PQ_WPTR_POLL_CNTL 0xC20C
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#define WPTR_POLL_EN (1 << 31)
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#define CPC_INT_CNTL 0xC2D0
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#define CP_ME1_PIPE0_INT_CNTL 0xC214
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#define CP_ME1_PIPE1_INT_CNTL 0xC218
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#define CP_ME1_PIPE2_INT_CNTL 0xC21C
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#define CP_ME1_PIPE3_INT_CNTL 0xC220
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#define CP_ME2_PIPE0_INT_CNTL 0xC224
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#define CP_ME2_PIPE1_INT_CNTL 0xC228
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#define CP_ME2_PIPE2_INT_CNTL 0xC22C
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#define CP_ME2_PIPE3_INT_CNTL 0xC230
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#define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
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#define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
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#define PRIV_REG_INT_ENABLE (1 << 23)
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#define TIME_STAMP_INT_ENABLE (1 << 26)
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#define GENERIC2_INT_ENABLE (1 << 29)
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#define GENERIC1_INT_ENABLE (1 << 30)
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#define GENERIC0_INT_ENABLE (1 << 31)
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#define CP_ME1_PIPE0_INT_STATUS 0xC214
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#define CP_ME1_PIPE1_INT_STATUS 0xC218
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#define CP_ME1_PIPE2_INT_STATUS 0xC21C
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#define CP_ME1_PIPE3_INT_STATUS 0xC220
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#define CP_ME2_PIPE0_INT_STATUS 0xC224
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#define CP_ME2_PIPE1_INT_STATUS 0xC228
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#define CP_ME2_PIPE2_INT_STATUS 0xC22C
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#define CP_ME2_PIPE3_INT_STATUS 0xC230
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#define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
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#define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
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#define PRIV_REG_INT_STATUS (1 << 23)
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#define TIME_STAMP_INT_STATUS (1 << 26)
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#define GENERIC2_INT_STATUS (1 << 29)
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#define GENERIC1_INT_STATUS (1 << 30)
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#define GENERIC0_INT_STATUS (1 << 31)
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#define CP_HPD_EOP_BASE_ADDR 0xC904
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#define CP_HPD_EOP_BASE_ADDR_HI 0xC908
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#define CP_HPD_EOP_VMID 0xC90C
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#define CP_HPD_EOP_CONTROL 0xC910
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#define EOP_SIZE(x) ((x) << 0)
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#define EOP_SIZE_MASK (0x3f << 0)
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#define CP_MQD_BASE_ADDR 0xC914
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#define CP_MQD_BASE_ADDR_HI 0xC918
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#define CP_HQD_ACTIVE 0xC91C
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#define CP_HQD_VMID 0xC920
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#define CP_HQD_PERSISTENT_STATE 0xC924u
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#define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8)
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#define PRELOAD_REQ (1 << 0)
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#define CP_HQD_PIPE_PRIORITY 0xC928u
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#define CP_HQD_QUEUE_PRIORITY 0xC92Cu
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#define CP_HQD_QUANTUM 0xC930u
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#define QUANTUM_EN 1U
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#define QUANTUM_SCALE_1MS (1U << 4)
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#define QUANTUM_DURATION(x) ((x) << 8)
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#define CP_HQD_PQ_BASE 0xC934
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#define CP_HQD_PQ_BASE_HI 0xC938
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#define CP_HQD_PQ_RPTR 0xC93C
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#define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940
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#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944
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#define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948
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#define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C
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#define CP_HQD_PQ_DOORBELL_CONTROL 0xC950
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#define DOORBELL_OFFSET(x) ((x) << 2)
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#define DOORBELL_OFFSET_MASK (0x1fffff << 2)
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#define DOORBELL_SOURCE (1 << 28)
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#define DOORBELL_SCHD_HIT (1 << 29)
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#define DOORBELL_EN (1 << 30)
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#define DOORBELL_HIT (1 << 31)
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#define CP_HQD_PQ_WPTR 0xC954
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#define CP_HQD_PQ_CONTROL 0xC958
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#define QUEUE_SIZE(x) ((x) << 0)
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#define QUEUE_SIZE_MASK (0x3f << 0)
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#define RPTR_BLOCK_SIZE(x) ((x) << 8)
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#define RPTR_BLOCK_SIZE_MASK (0x3f << 8)
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#define MIN_AVAIL_SIZE(x) ((x) << 20)
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#define PQ_ATC_EN (1 << 23)
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#define PQ_VOLATILE (1 << 26)
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#define NO_UPDATE_RPTR (1 << 27)
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#define UNORD_DISPATCH (1 << 28)
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#define ROQ_PQ_IB_FLIP (1 << 29)
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#define PRIV_STATE (1 << 30)
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#define KMD_QUEUE (1 << 31)
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#define DEFAULT_RPTR_BLOCK_SIZE RPTR_BLOCK_SIZE(5)
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#define DEFAULT_MIN_AVAIL_SIZE MIN_AVAIL_SIZE(3)
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#define CP_HQD_IB_BASE_ADDR 0xC95Cu
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#define CP_HQD_IB_BASE_ADDR_HI 0xC960u
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#define CP_HQD_IB_RPTR 0xC964u
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#define CP_HQD_IB_CONTROL 0xC968u
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#define IB_ATC_EN (1U << 23)
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#define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20)
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#define CP_HQD_DEQUEUE_REQUEST 0xC974
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#define DEQUEUE_REQUEST_DRAIN 1
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#define DEQUEUE_REQUEST_RESET 2
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#define DEQUEUE_INT (1U << 8)
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#define CP_HQD_SEMA_CMD 0xC97Cu
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#define CP_HQD_MSG_TYPE 0xC980u
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#define CP_HQD_ATOMIC0_PREOP_LO 0xC984u
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#define CP_HQD_ATOMIC0_PREOP_HI 0xC988u
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#define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu
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#define CP_HQD_ATOMIC1_PREOP_HI 0xC990u
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#define CP_HQD_HQ_SCHEDULER0 0xC994u
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#define CP_HQD_HQ_SCHEDULER1 0xC998u
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#define CP_MQD_CONTROL 0xC99C
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#define MQD_VMID(x) ((x) << 0)
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#define MQD_VMID_MASK (0xf << 0)
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#define MQD_CONTROL_PRIV_STATE_EN (1U << 8)
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#define GRBM_GFX_INDEX 0x30800
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#define INSTANCE_INDEX(x) ((x) << 0)
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#define SH_INDEX(x) ((x) << 8)
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#define SE_INDEX(x) ((x) << 16)
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#define SH_BROADCAST_WRITES (1 << 29)
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#define INSTANCE_BROADCAST_WRITES (1 << 30)
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#define SE_BROADCAST_WRITES (1 << 31)
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#define SQC_CACHES 0x30d20
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#define SQC_POLICY 0x8C38u
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#define SQC_VOLATILE 0x8C3Cu
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#define CP_PERFMON_CNTL 0x36020
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#define ATC_VMID0_PASID_MAPPING 0x339Cu
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#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u
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#define ATC_VMID_PASID_MAPPING_VALID (1U << 31)
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#define ATC_VM_APERTURE0_CNTL 0x3310u
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#define ATS_ACCESS_MODE_NEVER 0
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#define ATS_ACCESS_MODE_ALWAYS 1
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#define ATC_VM_APERTURE0_CNTL2 0x3318u
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#define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u
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#define ATC_VM_APERTURE0_LOW_ADDR 0x3300u
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#define ATC_VM_APERTURE1_CNTL 0x3314u
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#define ATC_VM_APERTURE1_CNTL2 0x331Cu
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#define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu
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#define ATC_VM_APERTURE1_LOW_ADDR 0x3304u
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#endif
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@ -0,0 +1,346 @@
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/printk.h>
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#include <linux/slab.h>
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#include "kfd_priv.h"
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#include "kfd_mqd_manager.h"
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#include "cik_regs.h"
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#include "../../radeon/cik_reg.h"
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inline void busy_wait(unsigned long ms)
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{
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while (time_before(jiffies, ms))
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cpu_relax();
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}
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static inline struct cik_mqd *get_mqd(void *mqd)
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{
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return (struct cik_mqd *)mqd;
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}
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static int init_mqd(struct mqd_manager *mm, void **mqd,
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struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
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struct queue_properties *q)
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{
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uint64_t addr;
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struct cik_mqd *m;
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int retval;
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BUG_ON(!mm || !q || !mqd);
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pr_debug("kfd: In func %s\n", __func__);
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retval = kfd2kgd->allocate_mem(mm->dev->kgd,
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sizeof(struct cik_mqd),
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256,
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KFD_MEMPOOL_SYSTEM_WRITECOMBINE,
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(struct kgd_mem **) mqd_mem_obj);
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if (retval != 0)
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return -ENOMEM;
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m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr;
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addr = (*mqd_mem_obj)->gpu_addr;
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memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256));
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m->header = 0xC0310800;
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m->compute_pipelinestat_enable = 1;
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m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
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m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
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m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
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m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
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/*
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* Make sure to use the last queue state saved on mqd when the cp
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* reassigns the queue, so when queue is switched on/off (e.g over
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* subscription or quantum timeout) the context will be consistent
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*/
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m->cp_hqd_persistent_state =
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DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ;
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m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN;
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m->cp_mqd_base_addr_lo = lower_32_bits(addr);
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m->cp_mqd_base_addr_hi = upper_32_bits(addr);
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m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE | IB_ATC_EN;
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/* Although WinKFD writes this, I suspect it should not be necessary */
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m->cp_hqd_ib_control = IB_ATC_EN | DEFAULT_MIN_IB_AVAIL_SIZE;
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m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS |
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QUANTUM_DURATION(10);
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/*
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* Pipe Priority
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* Identifies the pipe relative priority when this queue is connected
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* to the pipeline. The pipe priority is against the GFX pipe and HP3D.
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* In KFD we are using a fixed pipe priority set to CS_MEDIUM.
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* 0 = CS_LOW (typically below GFX)
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* 1 = CS_MEDIUM (typically between HP3D and GFX
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* 2 = CS_HIGH (typically above HP3D)
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*/
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m->cp_hqd_pipe_priority = 1;
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m->cp_hqd_queue_priority = 15;
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*mqd = m;
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if (gart_addr != NULL)
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*gart_addr = addr;
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retval = mm->update_mqd(mm, m, q);
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return retval;
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}
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static void uninit_mqd(struct mqd_manager *mm, void *mqd,
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struct kfd_mem_obj *mqd_mem_obj)
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{
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BUG_ON(!mm || !mqd);
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kfd2kgd->free_mem(mm->dev->kgd, (struct kgd_mem *) mqd_mem_obj);
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}
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static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr)
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{
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return kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, wptr);
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}
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static int update_mqd(struct mqd_manager *mm, void *mqd,
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struct queue_properties *q)
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{
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struct cik_mqd *m;
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BUG_ON(!mm || !q || !mqd);
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pr_debug("kfd: In func %s\n", __func__);
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m = get_mqd(mqd);
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m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE |
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DEFAULT_MIN_AVAIL_SIZE | PQ_ATC_EN;
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/*
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* Calculating queue size which is log base 2 of actual queue size -1
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* dwords and another -1 for ffs
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*/
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m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int))
|
||||
- 1 - 1;
|
||||
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
|
||||
m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
|
||||
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
|
||||
m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
|
||||
m->cp_hqd_pq_doorbell_control = DOORBELL_EN |
|
||||
DOORBELL_OFFSET(q->doorbell_off);
|
||||
|
||||
m->cp_hqd_vmid = q->vmid;
|
||||
|
||||
if (q->format == KFD_QUEUE_FORMAT_AQL) {
|
||||
m->cp_hqd_iq_rptr = AQL_ENABLE;
|
||||
m->cp_hqd_pq_control |= NO_UPDATE_RPTR;
|
||||
}
|
||||
|
||||
m->cp_hqd_active = 0;
|
||||
q->is_active = false;
|
||||
if (q->queue_size > 0 &&
|
||||
q->queue_address != 0 &&
|
||||
q->queue_percent > 0) {
|
||||
m->cp_hqd_active = 1;
|
||||
q->is_active = true;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int destroy_mqd(struct mqd_manager *mm, void *mqd,
|
||||
enum kfd_preempt_type type,
|
||||
unsigned int timeout, uint32_t pipe_id,
|
||||
uint32_t queue_id)
|
||||
{
|
||||
return kfd2kgd->hqd_destroy(mm->dev->kgd, type, timeout,
|
||||
pipe_id, queue_id);
|
||||
}
|
||||
|
||||
bool is_occupied(struct mqd_manager *mm, void *mqd,
|
||||
uint64_t queue_address, uint32_t pipe_id,
|
||||
uint32_t queue_id)
|
||||
{
|
||||
|
||||
return kfd2kgd->hqd_is_occupies(mm->dev->kgd, queue_address,
|
||||
pipe_id, queue_id);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* HIQ MQD Implementation, concrete implementation for HIQ MQD implementation.
|
||||
* The HIQ queue in Kaveri is using the same MQD structure as all the user mode
|
||||
* queues but with different initial values.
|
||||
*/
|
||||
|
||||
static int init_mqd_hiq(struct mqd_manager *mm, void **mqd,
|
||||
struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
|
||||
struct queue_properties *q)
|
||||
{
|
||||
uint64_t addr;
|
||||
struct cik_mqd *m;
|
||||
int retval;
|
||||
|
||||
BUG_ON(!mm || !q || !mqd || !mqd_mem_obj);
|
||||
|
||||
pr_debug("kfd: In func %s\n", __func__);
|
||||
|
||||
retval = kfd2kgd->allocate_mem(mm->dev->kgd,
|
||||
sizeof(struct cik_mqd),
|
||||
256,
|
||||
KFD_MEMPOOL_SYSTEM_WRITECOMBINE,
|
||||
(struct kgd_mem **) mqd_mem_obj);
|
||||
|
||||
if (retval != 0)
|
||||
return -ENOMEM;
|
||||
|
||||
m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr;
|
||||
addr = (*mqd_mem_obj)->gpu_addr;
|
||||
|
||||
memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256));
|
||||
|
||||
m->header = 0xC0310800;
|
||||
m->compute_pipelinestat_enable = 1;
|
||||
m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
|
||||
m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
|
||||
m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
|
||||
m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
|
||||
|
||||
m->cp_hqd_persistent_state = DEFAULT_CP_HQD_PERSISTENT_STATE |
|
||||
PRELOAD_REQ;
|
||||
m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS |
|
||||
QUANTUM_DURATION(10);
|
||||
|
||||
m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN;
|
||||
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
|
||||
m->cp_mqd_base_addr_hi = upper_32_bits(addr);
|
||||
|
||||
m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE;
|
||||
|
||||
/*
|
||||
* Pipe Priority
|
||||
* Identifies the pipe relative priority when this queue is connected
|
||||
* to the pipeline. The pipe priority is against the GFX pipe and HP3D.
|
||||
* In KFD we are using a fixed pipe priority set to CS_MEDIUM.
|
||||
* 0 = CS_LOW (typically below GFX)
|
||||
* 1 = CS_MEDIUM (typically between HP3D and GFX
|
||||
* 2 = CS_HIGH (typically above HP3D)
|
||||
*/
|
||||
m->cp_hqd_pipe_priority = 1;
|
||||
m->cp_hqd_queue_priority = 15;
|
||||
|
||||
*mqd = m;
|
||||
if (gart_addr)
|
||||
*gart_addr = addr;
|
||||
retval = mm->update_mqd(mm, m, q);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
|
||||
struct queue_properties *q)
|
||||
{
|
||||
struct cik_mqd *m;
|
||||
|
||||
BUG_ON(!mm || !q || !mqd);
|
||||
|
||||
pr_debug("kfd: In func %s\n", __func__);
|
||||
|
||||
m = get_mqd(mqd);
|
||||
m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE |
|
||||
DEFAULT_MIN_AVAIL_SIZE |
|
||||
PRIV_STATE |
|
||||
KMD_QUEUE;
|
||||
|
||||
/*
|
||||
* Calculating queue size which is log base 2 of actual queue
|
||||
* size -1 dwords
|
||||
*/
|
||||
m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int))
|
||||
- 1 - 1;
|
||||
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
|
||||
m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
|
||||
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
|
||||
m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
|
||||
m->cp_hqd_pq_doorbell_control = DOORBELL_EN |
|
||||
DOORBELL_OFFSET(q->doorbell_off);
|
||||
|
||||
m->cp_hqd_vmid = q->vmid;
|
||||
|
||||
m->cp_hqd_active = 0;
|
||||
q->is_active = false;
|
||||
if (q->queue_size > 0 &&
|
||||
q->queue_address != 0 &&
|
||||
q->queue_percent > 0) {
|
||||
m->cp_hqd_active = 1;
|
||||
q->is_active = true;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct mqd_manager *mqd_manager_init(enum KFD_MQD_TYPE type,
|
||||
struct kfd_dev *dev)
|
||||
{
|
||||
struct mqd_manager *mqd;
|
||||
|
||||
BUG_ON(!dev);
|
||||
BUG_ON(type >= KFD_MQD_TYPE_MAX);
|
||||
|
||||
pr_debug("kfd: In func %s\n", __func__);
|
||||
|
||||
mqd = kzalloc(sizeof(struct mqd_manager), GFP_KERNEL);
|
||||
if (!mqd)
|
||||
return NULL;
|
||||
|
||||
mqd->dev = dev;
|
||||
|
||||
switch (type) {
|
||||
case KFD_MQD_TYPE_CIK_CP:
|
||||
case KFD_MQD_TYPE_CIK_COMPUTE:
|
||||
mqd->init_mqd = init_mqd;
|
||||
mqd->uninit_mqd = uninit_mqd;
|
||||
mqd->load_mqd = load_mqd;
|
||||
mqd->update_mqd = update_mqd;
|
||||
mqd->destroy_mqd = destroy_mqd;
|
||||
mqd->is_occupied = is_occupied;
|
||||
break;
|
||||
case KFD_MQD_TYPE_CIK_HIQ:
|
||||
mqd->init_mqd = init_mqd_hiq;
|
||||
mqd->uninit_mqd = uninit_mqd;
|
||||
mqd->load_mqd = load_mqd;
|
||||
mqd->update_mqd = update_mqd_hiq;
|
||||
mqd->destroy_mqd = destroy_mqd;
|
||||
mqd->is_occupied = is_occupied;
|
||||
break;
|
||||
default:
|
||||
kfree(mqd);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return mqd;
|
||||
}
|
||||
|
||||
/* SDMA queues should be implemented here when the cp will supports them */
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* Copyright 2014 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef KFD_MQD_MANAGER_H_
|
||||
#define KFD_MQD_MANAGER_H_
|
||||
|
||||
#include "kfd_priv.h"
|
||||
|
||||
/**
|
||||
* struct mqd_manager
|
||||
*
|
||||
* @init_mqd: Allocates the mqd buffer on local gpu memory and initialize it.
|
||||
*
|
||||
* @load_mqd: Loads the mqd to a concrete hqd slot. Used only for no cp
|
||||
* scheduling mode.
|
||||
*
|
||||
* @update_mqd: Handles a update call for the MQD
|
||||
*
|
||||
* @destroy_mqd: Destroys the HQD slot and by that preempt the relevant queue.
|
||||
* Used only for no cp scheduling.
|
||||
*
|
||||
* @uninit_mqd: Releases the mqd buffer from local gpu memory.
|
||||
*
|
||||
* @is_occupied: Checks if the relevant HQD slot is occupied.
|
||||
*
|
||||
* @mqd_mutex: Mqd manager mutex.
|
||||
*
|
||||
* @dev: The kfd device structure coupled with this module.
|
||||
*
|
||||
* MQD stands for Memory Queue Descriptor which represents the current queue
|
||||
* state in the memory and initiate the HQD (Hardware Queue Descriptor) state.
|
||||
* This structure is actually a base class for the different types of MQDs
|
||||
* structures for the variant ASICs that should be supported in the future.
|
||||
* This base class is also contains all the MQD specific operations.
|
||||
* Another important thing to mention is that each queue has a MQD that keeps
|
||||
* his state (or context) after each preemption or reassignment.
|
||||
* Basically there are a instances of the mqd manager class per MQD type per
|
||||
* ASIC. Currently the kfd driver supports only Kaveri so there are instances
|
||||
* per KFD_MQD_TYPE for each device.
|
||||
*
|
||||
*/
|
||||
|
||||
struct mqd_manager {
|
||||
int (*init_mqd)(struct mqd_manager *mm, void **mqd,
|
||||
struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
|
||||
struct queue_properties *q);
|
||||
|
||||
int (*load_mqd)(struct mqd_manager *mm, void *mqd,
|
||||
uint32_t pipe_id, uint32_t queue_id,
|
||||
uint32_t __user *wptr);
|
||||
|
||||
int (*update_mqd)(struct mqd_manager *mm, void *mqd,
|
||||
struct queue_properties *q);
|
||||
|
||||
int (*destroy_mqd)(struct mqd_manager *mm, void *mqd,
|
||||
enum kfd_preempt_type type,
|
||||
unsigned int timeout, uint32_t pipe_id,
|
||||
uint32_t queue_id);
|
||||
|
||||
void (*uninit_mqd)(struct mqd_manager *mm, void *mqd,
|
||||
struct kfd_mem_obj *mqd_mem_obj);
|
||||
|
||||
bool (*is_occupied)(struct mqd_manager *mm, void *mqd,
|
||||
uint64_t queue_address, uint32_t pipe_id,
|
||||
uint32_t queue_id);
|
||||
|
||||
struct mutex mqd_mutex;
|
||||
struct kfd_dev *dev;
|
||||
};
|
||||
|
||||
#endif /* KFD_MQD_MANAGER_H_ */
|
||||
|
|
@ -119,6 +119,11 @@ void kfd_chardev_exit(void);
|
|||
struct device *kfd_chardev(void);
|
||||
|
||||
|
||||
enum kfd_preempt_type {
|
||||
KFD_PREEMPT_TYPE_WAVEFRONT,
|
||||
KFD_PREEMPT_TYPE_WAVEFRONT_RESET
|
||||
};
|
||||
|
||||
/**
|
||||
* enum kfd_queue_type
|
||||
*
|
||||
|
|
@ -137,6 +142,11 @@ enum kfd_queue_type {
|
|||
KFD_QUEUE_TYPE_DIQ
|
||||
};
|
||||
|
||||
enum kfd_queue_format {
|
||||
KFD_QUEUE_FORMAT_PM4,
|
||||
KFD_QUEUE_FORMAT_AQL
|
||||
};
|
||||
|
||||
/**
|
||||
* struct queue_properties
|
||||
*
|
||||
|
|
@ -183,6 +193,7 @@ enum kfd_queue_type {
|
|||
*/
|
||||
struct queue_properties {
|
||||
enum kfd_queue_type type;
|
||||
enum kfd_queue_format format;
|
||||
unsigned int queue_id;
|
||||
uint64_t queue_address;
|
||||
uint64_t queue_size;
|
||||
|
|
@ -242,6 +253,17 @@ struct queue {
|
|||
struct kfd_dev *device;
|
||||
};
|
||||
|
||||
/*
|
||||
* Please read the kfd_mqd_manager.h description.
|
||||
*/
|
||||
enum KFD_MQD_TYPE {
|
||||
KFD_MQD_TYPE_CIK_COMPUTE = 0, /* for no cp scheduling */
|
||||
KFD_MQD_TYPE_CIK_HIQ, /* for hiq */
|
||||
KFD_MQD_TYPE_CIK_CP, /* for cp queues and diq */
|
||||
KFD_MQD_TYPE_CIK_SDMA, /* for sdma queues */
|
||||
KFD_MQD_TYPE_MAX
|
||||
};
|
||||
|
||||
/* Data that is per-process-per device. */
|
||||
struct kfd_process_device {
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in New Issue