ALSA: hda - Relocate RIRB/CORB interface to hda_controller
This is done to allow an HDA platform driver to reuse the code. A few of the interfaces added to hda_controller will disappear in following commits as their users are also moved to hda_controller. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Dylan Reid
Takashi Iwai
parent
2b5fd6c2e9
commit
6e85dddc1c
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@ -1023,6 +1023,391 @@ int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
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}
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EXPORT_SYMBOL_GPL(azx_attach_pcm_stream);
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/*
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* CORB / RIRB interface
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*/
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int azx_alloc_cmd_io(struct azx *chip)
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{
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int err;
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/* single page (at least 4096 bytes) must suffice for both ringbuffes */
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err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
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PAGE_SIZE, &chip->rb);
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if (err < 0)
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dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
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return err;
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}
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EXPORT_SYMBOL_GPL(azx_alloc_cmd_io);
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void azx_init_cmd_io(struct azx *chip)
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{
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int timeout;
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spin_lock_irq(&chip->reg_lock);
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/* CORB set up */
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chip->corb.addr = chip->rb.addr;
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chip->corb.buf = (u32 *)chip->rb.area;
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azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
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azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
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/* set the corb size to 256 entries (ULI requires explicitly) */
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azx_writeb(chip, CORBSIZE, 0x02);
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/* set the corb write pointer to 0 */
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azx_writew(chip, CORBWP, 0);
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/* reset the corb hw read pointer */
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azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
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for (timeout = 1000; timeout > 0; timeout--) {
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if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST)
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break;
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udelay(1);
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}
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if (timeout <= 0)
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dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
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azx_readw(chip, CORBRP));
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azx_writew(chip, CORBRP, 0);
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for (timeout = 1000; timeout > 0; timeout--) {
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if (azx_readw(chip, CORBRP) == 0)
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break;
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udelay(1);
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}
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if (timeout <= 0)
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dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
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azx_readw(chip, CORBRP));
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/* enable corb dma */
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azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
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/* RIRB set up */
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chip->rirb.addr = chip->rb.addr + 2048;
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chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
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chip->rirb.wp = chip->rirb.rp = 0;
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memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
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azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
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azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
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/* set the rirb size to 256 entries (ULI requires explicitly) */
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azx_writeb(chip, RIRBSIZE, 0x02);
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/* reset the rirb hw write pointer */
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azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
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/* set N=1, get RIRB response interrupt for new entry */
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if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
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azx_writew(chip, RINTCNT, 0xc0);
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else
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azx_writew(chip, RINTCNT, 1);
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/* enable rirb dma and response irq */
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azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
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spin_unlock_irq(&chip->reg_lock);
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}
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EXPORT_SYMBOL_GPL(azx_init_cmd_io);
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void azx_free_cmd_io(struct azx *chip)
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{
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spin_lock_irq(&chip->reg_lock);
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/* disable ringbuffer DMAs */
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azx_writeb(chip, RIRBCTL, 0);
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azx_writeb(chip, CORBCTL, 0);
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spin_unlock_irq(&chip->reg_lock);
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}
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EXPORT_SYMBOL_GPL(azx_free_cmd_io);
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static unsigned int azx_command_addr(u32 cmd)
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{
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unsigned int addr = cmd >> 28;
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if (addr >= AZX_MAX_CODECS) {
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snd_BUG();
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addr = 0;
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}
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return addr;
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}
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/* send a command */
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static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
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{
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struct azx *chip = bus->private_data;
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unsigned int addr = azx_command_addr(val);
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unsigned int wp, rp;
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spin_lock_irq(&chip->reg_lock);
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/* add command to corb */
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wp = azx_readw(chip, CORBWP);
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if (wp == 0xffff) {
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/* something wrong, controller likely turned to D3 */
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spin_unlock_irq(&chip->reg_lock);
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return -EIO;
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}
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wp++;
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wp %= ICH6_MAX_CORB_ENTRIES;
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rp = azx_readw(chip, CORBRP);
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if (wp == rp) {
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/* oops, it's full */
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spin_unlock_irq(&chip->reg_lock);
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return -EAGAIN;
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}
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chip->rirb.cmds[addr]++;
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chip->corb.buf[wp] = cpu_to_le32(val);
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azx_writew(chip, CORBWP, wp);
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spin_unlock_irq(&chip->reg_lock);
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return 0;
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}
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#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
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/* retrieve RIRB entry - called from interrupt handler */
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void azx_update_rirb(struct azx *chip)
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{
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unsigned int rp, wp;
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unsigned int addr;
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u32 res, res_ex;
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wp = azx_readw(chip, RIRBWP);
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if (wp == 0xffff) {
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/* something wrong, controller likely turned to D3 */
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return;
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}
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if (wp == chip->rirb.wp)
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return;
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chip->rirb.wp = wp;
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while (chip->rirb.rp != wp) {
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chip->rirb.rp++;
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chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
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rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
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res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
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res = le32_to_cpu(chip->rirb.buf[rp]);
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addr = res_ex & 0xf;
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if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
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dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
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res, res_ex,
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chip->rirb.rp, wp);
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snd_BUG();
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}
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else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
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snd_hda_queue_unsol_event(chip->bus, res, res_ex);
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else if (chip->rirb.cmds[addr]) {
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chip->rirb.res[addr] = res;
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smp_wmb();
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chip->rirb.cmds[addr]--;
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} else if (printk_ratelimit()) {
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dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
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res, res_ex,
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chip->last_cmd[addr]);
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}
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}
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}
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EXPORT_SYMBOL_GPL(azx_update_rirb);
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/* receive a response */
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static unsigned int azx_rirb_get_response(struct hda_bus *bus,
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unsigned int addr)
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{
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struct azx *chip = bus->private_data;
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unsigned long timeout;
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unsigned long loopcounter;
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int do_poll = 0;
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again:
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timeout = jiffies + msecs_to_jiffies(1000);
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for (loopcounter = 0;; loopcounter++) {
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if (chip->polling_mode || do_poll) {
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spin_lock_irq(&chip->reg_lock);
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azx_update_rirb(chip);
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spin_unlock_irq(&chip->reg_lock);
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}
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if (!chip->rirb.cmds[addr]) {
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smp_rmb();
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bus->rirb_error = 0;
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if (!do_poll)
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chip->poll_count = 0;
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return chip->rirb.res[addr]; /* the last value */
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}
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if (time_after(jiffies, timeout))
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break;
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if (bus->needs_damn_long_delay || loopcounter > 3000)
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msleep(2); /* temporary workaround */
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else {
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udelay(10);
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cond_resched();
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}
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}
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if (!bus->no_response_fallback)
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return -1;
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if (!chip->polling_mode && chip->poll_count < 2) {
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dev_dbg(chip->card->dev,
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"azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
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chip->last_cmd[addr]);
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do_poll = 1;
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chip->poll_count++;
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goto again;
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}
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if (!chip->polling_mode) {
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dev_warn(chip->card->dev,
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"azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
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chip->last_cmd[addr]);
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chip->polling_mode = 1;
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goto again;
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}
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if (chip->msi) {
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dev_warn(chip->card->dev,
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"No response from codec, disabling MSI: last cmd=0x%08x\n",
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chip->last_cmd[addr]);
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if (chip->ops->disable_msi_reset_irq(chip) &&
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chip->ops->disable_msi_reset_irq(chip) < 0) {
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bus->rirb_error = 1;
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return -1;
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}
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goto again;
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}
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if (chip->probing) {
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/* If this critical timeout happens during the codec probing
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* phase, this is likely an access to a non-existing codec
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* slot. Better to return an error and reset the system.
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*/
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return -1;
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}
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/* a fatal communication error; need either to reset or to fallback
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* to the single_cmd mode
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*/
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bus->rirb_error = 1;
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if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
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bus->response_reset = 1;
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return -1; /* give a chance to retry */
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}
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dev_err(chip->card->dev,
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"azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
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chip->last_cmd[addr]);
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chip->single_cmd = 1;
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bus->response_reset = 0;
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/* release CORB/RIRB */
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azx_free_cmd_io(chip);
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/* disable unsolicited responses */
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
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return -1;
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}
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/*
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* Use the single immediate command instead of CORB/RIRB for simplicity
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*
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* Note: according to Intel, this is not preferred use. The command was
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* intended for the BIOS only, and may get confused with unsolicited
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* responses. So, we shouldn't use it for normal operation from the
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* driver.
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* I left the codes, however, for debugging/testing purposes.
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*/
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/* receive a response */
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static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
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{
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int timeout = 50;
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while (timeout--) {
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/* check IRV busy bit */
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if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
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/* reuse rirb.res as the response return value */
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chip->rirb.res[addr] = azx_readl(chip, IR);
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return 0;
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}
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udelay(1);
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}
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if (printk_ratelimit())
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dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
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azx_readw(chip, IRS));
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chip->rirb.res[addr] = -1;
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return -EIO;
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}
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/* send a command */
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static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
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{
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struct azx *chip = bus->private_data;
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unsigned int addr = azx_command_addr(val);
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int timeout = 50;
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bus->rirb_error = 0;
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while (timeout--) {
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/* check ICB busy bit */
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if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
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/* Clear IRV valid bit */
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azx_writew(chip, IRS, azx_readw(chip, IRS) |
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ICH6_IRS_VALID);
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azx_writel(chip, IC, val);
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azx_writew(chip, IRS, azx_readw(chip, IRS) |
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ICH6_IRS_BUSY);
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return azx_single_wait_for_response(chip, addr);
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}
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udelay(1);
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}
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if (printk_ratelimit())
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dev_dbg(chip->card->dev,
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"send_cmd timeout: IRS=0x%x, val=0x%x\n",
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azx_readw(chip, IRS), val);
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return -EIO;
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}
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/* receive a response */
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static unsigned int azx_single_get_response(struct hda_bus *bus,
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unsigned int addr)
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{
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struct azx *chip = bus->private_data;
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return chip->rirb.res[addr];
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}
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/*
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* The below are the main callbacks from hda_codec.
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*
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* They are just the skeleton to call sub-callbacks according to the
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* current setting of chip->single_cmd.
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*/
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/* send a command */
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int azx_send_cmd(struct hda_bus *bus, unsigned int val)
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{
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struct azx *chip = bus->private_data;
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if (chip->disabled)
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return 0;
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chip->last_cmd[azx_command_addr(val)] = val;
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if (chip->single_cmd)
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return azx_single_send_cmd(bus, val);
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else
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return azx_corb_send_cmd(bus, val);
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}
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EXPORT_SYMBOL_GPL(azx_send_cmd);
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/* get a response */
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unsigned int azx_get_response(struct hda_bus *bus,
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unsigned int addr)
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{
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struct azx *chip = bus->private_data;
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if (chip->disabled)
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return 0;
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if (chip->single_cmd)
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return azx_single_get_response(bus, addr);
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else
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return azx_rirb_get_response(bus, addr);
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}
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EXPORT_SYMBOL_GPL(azx_get_response);
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#ifdef CONFIG_SND_HDA_DSP_LOADER
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/*
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* DSP loading code (e.g. for CA0132)
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@ -47,4 +47,15 @@ void azx_load_dsp_cleanup(struct hda_bus *bus,
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int azx_alloc_stream_pages(struct azx *chip);
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void azx_free_stream_pages(struct azx *chip);
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/*
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* CORB / RIRB interface
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*/
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int azx_alloc_cmd_io(struct azx *chip);
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void azx_init_cmd_io(struct azx *chip);
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void azx_free_cmd_io(struct azx *chip);
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void azx_update_rirb(struct azx *chip);
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int azx_send_cmd(struct hda_bus *bus, unsigned int val);
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unsigned int azx_get_response(struct hda_bus *bus,
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unsigned int addr);
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#endif /* __SOUND_HDA_CONTROLLER_H */
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@ -335,389 +335,6 @@ static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
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#endif
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static int azx_acquire_irq(struct azx *chip, int do_disconnect);
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static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
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/*
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* Interface for HD codec
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*/
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/*
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* CORB / RIRB interface
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*/
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static int azx_alloc_cmd_io(struct azx *chip)
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{
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int err;
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/* single page (at least 4096 bytes) must suffice for both ringbuffes */
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err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
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PAGE_SIZE, &chip->rb);
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if (err < 0)
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dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
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return err;
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}
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static void azx_init_cmd_io(struct azx *chip)
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{
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int timeout;
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spin_lock_irq(&chip->reg_lock);
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/* CORB set up */
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chip->corb.addr = chip->rb.addr;
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chip->corb.buf = (u32 *)chip->rb.area;
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azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
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azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
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/* set the corb size to 256 entries (ULI requires explicitly) */
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azx_writeb(chip, CORBSIZE, 0x02);
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/* set the corb write pointer to 0 */
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azx_writew(chip, CORBWP, 0);
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/* reset the corb hw read pointer */
|
||||
azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
|
||||
for (timeout = 1000; timeout > 0; timeout--) {
|
||||
if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
if (timeout <= 0)
|
||||
dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
|
||||
azx_readw(chip, CORBRP));
|
||||
|
||||
azx_writew(chip, CORBRP, 0);
|
||||
for (timeout = 1000; timeout > 0; timeout--) {
|
||||
if (azx_readw(chip, CORBRP) == 0)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
if (timeout <= 0)
|
||||
dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
|
||||
azx_readw(chip, CORBRP));
|
||||
|
||||
/* enable corb dma */
|
||||
azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
|
||||
|
||||
/* RIRB set up */
|
||||
chip->rirb.addr = chip->rb.addr + 2048;
|
||||
chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
|
||||
chip->rirb.wp = chip->rirb.rp = 0;
|
||||
memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
|
||||
azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
|
||||
azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
|
||||
|
||||
/* set the rirb size to 256 entries (ULI requires explicitly) */
|
||||
azx_writeb(chip, RIRBSIZE, 0x02);
|
||||
/* reset the rirb hw write pointer */
|
||||
azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
|
||||
/* set N=1, get RIRB response interrupt for new entry */
|
||||
if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
|
||||
azx_writew(chip, RINTCNT, 0xc0);
|
||||
else
|
||||
azx_writew(chip, RINTCNT, 1);
|
||||
/* enable rirb dma and response irq */
|
||||
azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
}
|
||||
|
||||
static void azx_free_cmd_io(struct azx *chip)
|
||||
{
|
||||
spin_lock_irq(&chip->reg_lock);
|
||||
/* disable ringbuffer DMAs */
|
||||
azx_writeb(chip, RIRBCTL, 0);
|
||||
azx_writeb(chip, CORBCTL, 0);
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
}
|
||||
|
||||
static unsigned int azx_command_addr(u32 cmd)
|
||||
{
|
||||
unsigned int addr = cmd >> 28;
|
||||
|
||||
if (addr >= AZX_MAX_CODECS) {
|
||||
snd_BUG();
|
||||
addr = 0;
|
||||
}
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
/* send a command */
|
||||
static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
|
||||
{
|
||||
struct azx *chip = bus->private_data;
|
||||
unsigned int addr = azx_command_addr(val);
|
||||
unsigned int wp, rp;
|
||||
|
||||
spin_lock_irq(&chip->reg_lock);
|
||||
|
||||
/* add command to corb */
|
||||
wp = azx_readw(chip, CORBWP);
|
||||
if (wp == 0xffff) {
|
||||
/* something wrong, controller likely turned to D3 */
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
return -EIO;
|
||||
}
|
||||
wp++;
|
||||
wp %= ICH6_MAX_CORB_ENTRIES;
|
||||
|
||||
rp = azx_readw(chip, CORBRP);
|
||||
if (wp == rp) {
|
||||
/* oops, it's full */
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
chip->rirb.cmds[addr]++;
|
||||
chip->corb.buf[wp] = cpu_to_le32(val);
|
||||
azx_writew(chip, CORBWP, wp);
|
||||
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
|
||||
|
||||
/* retrieve RIRB entry - called from interrupt handler */
|
||||
static void azx_update_rirb(struct azx *chip)
|
||||
{
|
||||
unsigned int rp, wp;
|
||||
unsigned int addr;
|
||||
u32 res, res_ex;
|
||||
|
||||
wp = azx_readw(chip, RIRBWP);
|
||||
if (wp == 0xffff) {
|
||||
/* something wrong, controller likely turned to D3 */
|
||||
return;
|
||||
}
|
||||
|
||||
if (wp == chip->rirb.wp)
|
||||
return;
|
||||
chip->rirb.wp = wp;
|
||||
|
||||
while (chip->rirb.rp != wp) {
|
||||
chip->rirb.rp++;
|
||||
chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
|
||||
|
||||
rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
|
||||
res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
|
||||
res = le32_to_cpu(chip->rirb.buf[rp]);
|
||||
addr = res_ex & 0xf;
|
||||
if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
|
||||
dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
|
||||
res, res_ex,
|
||||
chip->rirb.rp, wp);
|
||||
snd_BUG();
|
||||
}
|
||||
else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
|
||||
snd_hda_queue_unsol_event(chip->bus, res, res_ex);
|
||||
else if (chip->rirb.cmds[addr]) {
|
||||
chip->rirb.res[addr] = res;
|
||||
smp_wmb();
|
||||
chip->rirb.cmds[addr]--;
|
||||
} else if (printk_ratelimit()) {
|
||||
dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
|
||||
res, res_ex,
|
||||
chip->last_cmd[addr]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* receive a response */
|
||||
static unsigned int azx_rirb_get_response(struct hda_bus *bus,
|
||||
unsigned int addr)
|
||||
{
|
||||
struct azx *chip = bus->private_data;
|
||||
unsigned long timeout;
|
||||
unsigned long loopcounter;
|
||||
int do_poll = 0;
|
||||
|
||||
again:
|
||||
timeout = jiffies + msecs_to_jiffies(1000);
|
||||
|
||||
for (loopcounter = 0;; loopcounter++) {
|
||||
if (chip->polling_mode || do_poll) {
|
||||
spin_lock_irq(&chip->reg_lock);
|
||||
azx_update_rirb(chip);
|
||||
spin_unlock_irq(&chip->reg_lock);
|
||||
}
|
||||
if (!chip->rirb.cmds[addr]) {
|
||||
smp_rmb();
|
||||
bus->rirb_error = 0;
|
||||
|
||||
if (!do_poll)
|
||||
chip->poll_count = 0;
|
||||
return chip->rirb.res[addr]; /* the last value */
|
||||
}
|
||||
if (time_after(jiffies, timeout))
|
||||
break;
|
||||
if (bus->needs_damn_long_delay || loopcounter > 3000)
|
||||
msleep(2); /* temporary workaround */
|
||||
else {
|
||||
udelay(10);
|
||||
cond_resched();
|
||||
}
|
||||
}
|
||||
|
||||
if (!bus->no_response_fallback)
|
||||
return -1;
|
||||
|
||||
if (!chip->polling_mode && chip->poll_count < 2) {
|
||||
dev_dbg(chip->card->dev,
|
||||
"azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
|
||||
chip->last_cmd[addr]);
|
||||
do_poll = 1;
|
||||
chip->poll_count++;
|
||||
goto again;
|
||||
}
|
||||
|
||||
|
||||
if (!chip->polling_mode) {
|
||||
dev_warn(chip->card->dev,
|
||||
"azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
|
||||
chip->last_cmd[addr]);
|
||||
chip->polling_mode = 1;
|
||||
goto again;
|
||||
}
|
||||
|
||||
if (chip->msi) {
|
||||
dev_warn(chip->card->dev,
|
||||
"No response from codec, disabling MSI: last cmd=0x%08x\n",
|
||||
chip->last_cmd[addr]);
|
||||
if (chip->ops->disable_msi_reset_irq &&
|
||||
chip->ops->disable_msi_reset_irq(chip) < 0) {
|
||||
bus->rirb_error = 1;
|
||||
return -1;
|
||||
}
|
||||
goto again;
|
||||
}
|
||||
|
||||
if (chip->probing) {
|
||||
/* If this critical timeout happens during the codec probing
|
||||
* phase, this is likely an access to a non-existing codec
|
||||
* slot. Better to return an error and reset the system.
|
||||
*/
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* a fatal communication error; need either to reset or to fallback
|
||||
* to the single_cmd mode
|
||||
*/
|
||||
bus->rirb_error = 1;
|
||||
if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
|
||||
bus->response_reset = 1;
|
||||
return -1; /* give a chance to retry */
|
||||
}
|
||||
|
||||
dev_err(chip->card->dev,
|
||||
"azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
|
||||
chip->last_cmd[addr]);
|
||||
chip->single_cmd = 1;
|
||||
bus->response_reset = 0;
|
||||
/* release CORB/RIRB */
|
||||
azx_free_cmd_io(chip);
|
||||
/* disable unsolicited responses */
|
||||
azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Use the single immediate command instead of CORB/RIRB for simplicity
|
||||
*
|
||||
* Note: according to Intel, this is not preferred use. The command was
|
||||
* intended for the BIOS only, and may get confused with unsolicited
|
||||
* responses. So, we shouldn't use it for normal operation from the
|
||||
* driver.
|
||||
* I left the codes, however, for debugging/testing purposes.
|
||||
*/
|
||||
|
||||
/* receive a response */
|
||||
static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
|
||||
{
|
||||
int timeout = 50;
|
||||
|
||||
while (timeout--) {
|
||||
/* check IRV busy bit */
|
||||
if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
|
||||
/* reuse rirb.res as the response return value */
|
||||
chip->rirb.res[addr] = azx_readl(chip, IR);
|
||||
return 0;
|
||||
}
|
||||
udelay(1);
|
||||
}
|
||||
if (printk_ratelimit())
|
||||
dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
|
||||
azx_readw(chip, IRS));
|
||||
chip->rirb.res[addr] = -1;
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* send a command */
|
||||
static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
|
||||
{
|
||||
struct azx *chip = bus->private_data;
|
||||
unsigned int addr = azx_command_addr(val);
|
||||
int timeout = 50;
|
||||
|
||||
bus->rirb_error = 0;
|
||||
while (timeout--) {
|
||||
/* check ICB busy bit */
|
||||
if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
|
||||
/* Clear IRV valid bit */
|
||||
azx_writew(chip, IRS, azx_readw(chip, IRS) |
|
||||
ICH6_IRS_VALID);
|
||||
azx_writel(chip, IC, val);
|
||||
azx_writew(chip, IRS, azx_readw(chip, IRS) |
|
||||
ICH6_IRS_BUSY);
|
||||
return azx_single_wait_for_response(chip, addr);
|
||||
}
|
||||
udelay(1);
|
||||
}
|
||||
if (printk_ratelimit())
|
||||
dev_dbg(chip->card->dev,
|
||||
"send_cmd timeout: IRS=0x%x, val=0x%x\n",
|
||||
azx_readw(chip, IRS), val);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* receive a response */
|
||||
static unsigned int azx_single_get_response(struct hda_bus *bus,
|
||||
unsigned int addr)
|
||||
{
|
||||
struct azx *chip = bus->private_data;
|
||||
return chip->rirb.res[addr];
|
||||
}
|
||||
|
||||
/*
|
||||
* The below are the main callbacks from hda_codec.
|
||||
*
|
||||
* They are just the skeleton to call sub-callbacks according to the
|
||||
* current setting of chip->single_cmd.
|
||||
*/
|
||||
|
||||
/* send a command */
|
||||
static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
|
||||
{
|
||||
struct azx *chip = bus->private_data;
|
||||
|
||||
if (chip->disabled)
|
||||
return 0;
|
||||
chip->last_cmd[azx_command_addr(val)] = val;
|
||||
if (chip->single_cmd)
|
||||
return azx_single_send_cmd(bus, val);
|
||||
else
|
||||
return azx_corb_send_cmd(bus, val);
|
||||
}
|
||||
|
||||
/* get a response */
|
||||
static unsigned int azx_get_response(struct hda_bus *bus,
|
||||
unsigned int addr)
|
||||
{
|
||||
struct azx *chip = bus->private_data;
|
||||
if (chip->disabled)
|
||||
return 0;
|
||||
if (chip->single_cmd)
|
||||
return azx_single_get_response(bus, addr);
|
||||
else
|
||||
return azx_rirb_get_response(bus, addr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static void azx_power_notify(struct hda_bus *bus, bool power_up);
|
||||
|
|
|
|||
Loading…
Reference in New Issue