RDMA/mlx5: set UMR wqe fence according to HCA cap
Cache the needed umr_fence and set the wqe ctrl segmennt accordingly. Signed-off-by: Max Gurtovoy <maxg@mellanox.com> Acked-by: Leon Romanovsky <leon@kernel.org> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Signed-off-by: Doug Ledford <dledford@redhat.com>
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1410a90ae4
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@ -2979,6 +2979,18 @@ error_0:
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return ret;
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}
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static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
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{
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switch (umr_fence_cap) {
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case MLX5_CAP_UMR_FENCE_NONE:
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return MLX5_FENCE_MODE_NONE;
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case MLX5_CAP_UMR_FENCE_SMALL:
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return MLX5_FENCE_MODE_INITIATOR_SMALL;
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default:
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return MLX5_FENCE_MODE_STRONG_ORDERING;
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}
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}
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static int create_dev_resources(struct mlx5_ib_resources *devr)
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{
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struct ib_srq_init_attr attr;
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@ -3693,6 +3705,8 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
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mlx5_ib_internal_fill_odp_caps(dev);
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dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
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if (MLX5_CAP_GEN(mdev, imaicl)) {
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dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
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dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
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@ -349,7 +349,7 @@ struct mlx5_ib_qp {
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struct mlx5_ib_wq rq;
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u8 sq_signal_bits;
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u8 fm_cache;
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u8 next_fence;
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struct mlx5_ib_wq sq;
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/* serialize qp state modifications
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@ -654,6 +654,7 @@ struct mlx5_ib_dev {
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struct mlx5_ib_port *port;
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struct mlx5_sq_bfreg bfreg;
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struct mlx5_sq_bfreg fp_bfreg;
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u8 umr_fence;
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};
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static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
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@ -3738,24 +3738,6 @@ static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
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}
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}
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static u8 get_fence(u8 fence, struct ib_send_wr *wr)
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{
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if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
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wr->send_flags & IB_SEND_FENCE))
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return MLX5_FENCE_MODE_STRONG_ORDERING;
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if (unlikely(fence)) {
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if (wr->send_flags & IB_SEND_FENCE)
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return MLX5_FENCE_MODE_SMALL_AND_FENCE;
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else
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return fence;
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} else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
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return MLX5_FENCE_MODE_FENCE;
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}
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return 0;
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}
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static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
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struct mlx5_wqe_ctrl_seg **ctrl,
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struct ib_send_wr *wr, unsigned *idx,
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@ -3784,8 +3766,7 @@ static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
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static void finish_wqe(struct mlx5_ib_qp *qp,
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struct mlx5_wqe_ctrl_seg *ctrl,
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u8 size, unsigned idx, u64 wr_id,
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int nreq, u8 fence, u8 next_fence,
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u32 mlx5_opcode)
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int nreq, u8 fence, u32 mlx5_opcode)
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{
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u8 opmod = 0;
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@ -3793,7 +3774,6 @@ static void finish_wqe(struct mlx5_ib_qp *qp,
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mlx5_opcode | ((u32)opmod << 24));
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ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
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ctrl->fm_ce_se |= fence;
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qp->fm_cache = next_fence;
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if (unlikely(qp->wq_sig))
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ctrl->signature = wq_sig(ctrl);
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@ -3853,7 +3833,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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goto out;
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}
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fence = qp->fm_cache;
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num_sge = wr->num_sge;
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if (unlikely(num_sge > qp->sq.max_gs)) {
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mlx5_ib_warn(dev, "\n");
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@ -3870,6 +3849,19 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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goto out;
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}
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if (wr->opcode == IB_WR_LOCAL_INV ||
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wr->opcode == IB_WR_REG_MR) {
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fence = dev->umr_fence;
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next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
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} else if (wr->send_flags & IB_SEND_FENCE) {
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if (qp->next_fence)
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fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
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else
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fence = MLX5_FENCE_MODE_FENCE;
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} else {
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fence = qp->next_fence;
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}
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switch (ibqp->qp_type) {
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case IB_QPT_XRC_INI:
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xrc = seg;
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@ -3896,7 +3888,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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goto out;
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case IB_WR_LOCAL_INV:
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next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
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qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
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ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
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set_linv_wr(qp, &seg, &size);
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@ -3904,7 +3895,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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break;
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case IB_WR_REG_MR:
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next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
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qp->sq.wr_data[idx] = IB_WR_REG_MR;
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ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
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err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
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@ -3927,9 +3917,8 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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goto out;
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}
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finish_wqe(qp, ctrl, size, idx, wr->wr_id,
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nreq, get_fence(fence, wr),
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next_fence, MLX5_OPCODE_UMR);
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finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
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fence, MLX5_OPCODE_UMR);
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/*
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* SET_PSV WQEs are not signaled and solicited
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* on error
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@ -3954,9 +3943,8 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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goto out;
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}
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finish_wqe(qp, ctrl, size, idx, wr->wr_id,
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nreq, get_fence(fence, wr),
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next_fence, MLX5_OPCODE_SET_PSV);
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finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
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fence, MLX5_OPCODE_SET_PSV);
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err = begin_wqe(qp, &seg, &ctrl, wr,
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&idx, &size, nreq);
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if (err) {
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@ -3966,7 +3954,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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goto out;
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}
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next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
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err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
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mr->sig->psv_wire.psv_idx, &seg,
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&size);
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@ -3976,9 +3963,9 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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goto out;
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}
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finish_wqe(qp, ctrl, size, idx, wr->wr_id,
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nreq, get_fence(fence, wr),
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next_fence, MLX5_OPCODE_SET_PSV);
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finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
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fence, MLX5_OPCODE_SET_PSV);
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qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
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num_sge = 0;
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goto skip_psv;
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@ -4089,8 +4076,8 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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}
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}
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finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
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get_fence(fence, wr), next_fence,
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qp->next_fence = next_fence;
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finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
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mlx5_ib_opcode[wr->opcode]);
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skip_psv:
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if (0)
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