[Blackfin] arch: Encourage users to use the spidev character driver: Provide platform support
- Enable kernel generic spidev driver for blackfin SPI ADC - spi_adc driver, document and test sample not synced Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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@ -517,6 +517,14 @@ static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
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.bits_per_word = 16,
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.bits_per_word = 16,
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};
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};
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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static struct bfin5xx_spi_chip spidev_chip_info = {
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.enable_dma = 0,
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.bits_per_word = 8,
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};
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#endif
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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#if defined(CONFIG_MTD_M25P80) \
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#if defined(CONFIG_MTD_M25P80) \
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|| defined(CONFIG_MTD_M25P80_MODULE)
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|| defined(CONFIG_MTD_M25P80_MODULE)
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@ -634,6 +642,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
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.mode = SPI_MODE_0,
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.mode = SPI_MODE_0,
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},
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},
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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{
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.modalias = "spidev",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 1,
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.controller_data = &spidev_chip_info,
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},
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#endif
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};
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};
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/* SPI controller data */
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/* SPI controller data */
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@ -134,6 +134,13 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
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};
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};
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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static struct bfin5xx_spi_chip spidev_chip_info = {
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.enable_dma = 0,
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.bits_per_word = 8,
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};
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#endif
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
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#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
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{
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{
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@ -168,6 +175,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
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.controller_data = &ad1836_spi_chip_info,
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.controller_data = &ad1836_spi_chip_info,
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},
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},
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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{
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.modalias = "spidev",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 1,
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.controller_data = &spidev_chip_info,
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},
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#endif
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};
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};
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/* SPI (0) */
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/* SPI (0) */
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@ -226,6 +226,13 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
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};
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};
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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static struct bfin5xx_spi_chip spidev_chip_info = {
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.enable_dma = 0,
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.bits_per_word = 8,
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};
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#endif
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
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#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
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{
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{
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@ -312,6 +319,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
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.mode = SPI_MODE_2,
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.mode = SPI_MODE_2,
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},
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},
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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{
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.modalias = "spidev",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 1,
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.controller_data = &spidev_chip_info,
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},
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#endif
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};
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};
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/* SPI (0) */
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/* SPI (0) */
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@ -487,6 +487,13 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
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};
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};
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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static struct bfin5xx_spi_chip spidev_chip_info = {
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.enable_dma = 0,
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.bits_per_word = 8,
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};
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#endif
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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#if defined(CONFIG_MTD_M25P80) \
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#if defined(CONFIG_MTD_M25P80) \
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|| defined(CONFIG_MTD_M25P80_MODULE)
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|| defined(CONFIG_MTD_M25P80_MODULE)
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@ -593,6 +600,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
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.controller_data = &spi_ad7877_chip_info,
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.controller_data = &spi_ad7877_chip_info,
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},
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},
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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{
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.modalias = "spidev",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 1,
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.controller_data = &spidev_chip_info,
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},
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#endif
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};
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};
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/* SPI controller data */
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/* SPI controller data */
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@ -420,6 +420,13 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
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};
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};
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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static struct bfin5xx_spi_chip spidev_chip_info = {
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.enable_dma = 0,
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.bits_per_word = 8,
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};
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#endif
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static struct spi_board_info bf54x_spi_board_info[] __initdata = {
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static struct spi_board_info bf54x_spi_board_info[] __initdata = {
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#if defined(CONFIG_MTD_M25P80) \
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#if defined(CONFIG_MTD_M25P80) \
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|| defined(CONFIG_MTD_M25P80_MODULE)
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|| defined(CONFIG_MTD_M25P80_MODULE)
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@ -445,6 +452,15 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
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.controller_data = &spi_ad7877_chip_info,
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.controller_data = &spi_ad7877_chip_info,
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},
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},
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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{
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.modalias = "spidev",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 1,
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.controller_data = &spidev_chip_info,
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},
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#endif
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};
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};
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/* SPI (0) */
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/* SPI (0) */
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@ -266,6 +266,13 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
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.bits_per_word = 16,
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.bits_per_word = 16,
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};
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};
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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static struct bfin5xx_spi_chip spidev_chip_info = {
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.enable_dma = 0,
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.bits_per_word = 8,
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};
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#endif
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#endif
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#endif
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/* SPI (0) */
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/* SPI (0) */
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@ -310,6 +317,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
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.controller_data = &ad1836_spi_chip_info,
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.controller_data = &ad1836_spi_chip_info,
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},
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},
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#endif
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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{
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.modalias = "spidev",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 1,
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.controller_data = &spidev_chip_info,
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},
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#endif
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};
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};
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#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
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#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
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@ -1,6 +1,6 @@
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/************************************************************
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/************************************************************
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*
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* Copyright (C) 2004, Analog Devices. All Rights Reserved
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* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
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*
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*
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* FILE bfin5xx_spi.h
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* FILE bfin5xx_spi.h
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* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
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* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
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@ -32,42 +32,6 @@
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#define SPI_BAUD_OFF 0x14
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#define SPI_BAUD_OFF 0x14
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#define SPI_SHAW_OFF 0x18
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#define SPI_SHAW_OFF 0x18
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#define CMD_SPI_OUT_ENABLE 1
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#define CMD_SPI_SET_BAUDRATE 2
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#define CMD_SPI_SET_POLAR 3
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#define CMD_SPI_SET_PHASE 4
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#define CMD_SPI_SET_MASTER 5
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#define CMD_SPI_SET_SENDOPT 6
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#define CMD_SPI_SET_RECVOPT 7
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#define CMD_SPI_SET_ORDER 8
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#define CMD_SPI_SET_LENGTH16 9
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#define CMD_SPI_GET_STAT 11
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#define CMD_SPI_GET_CFG 12
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#define CMD_SPI_SET_CSAVAIL 13
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#define CMD_SPI_SET_CSHIGH 14 /* CS unavail */
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#define CMD_SPI_SET_CSLOW 15 /* CS avail */
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#define CMD_SPI_MISO_ENABLE 16
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#define CMD_SPI_SET_CSENABLE 17
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#define CMD_SPI_SET_CSDISABLE 18
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#define CMD_SPI_SET_TRIGGER_MODE 19
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#define CMD_SPI_SET_TRIGGER_SENSE 20
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#define CMD_SPI_SET_TRIGGER_EDGE 21
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#define CMD_SPI_SET_TRIGGER_LEVEL 22
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#define CMD_SPI_SET_TIME_SPS 23
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#define CMD_SPI_SET_TIME_SAMPLES 24
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#define CMD_SPI_GET_SYSTEMCLOCK 25
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#define CMD_SPI_SET_WRITECONTINUOUS 26
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#define CMD_SPI_SET_SKFS 27
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#define CMD_SPI_GET_ALLCONFIG 32 /* For debug */
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#define SPI_DEFAULT_BARD 0x0100
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#define SPI0_IRQ_NUM IRQ_SPI
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#define SPI_ERR_TRIG -1
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#define BIT_CTL_ENABLE 0x4000
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#define BIT_CTL_ENABLE 0x4000
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#define BIT_CTL_OPENDRAIN 0x2000
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#define BIT_CTL_OPENDRAIN 0x2000
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@ -148,6 +112,10 @@
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#define CFG_SPI_CS6VALUE 6
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#define CFG_SPI_CS6VALUE 6
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#define CFG_SPI_CS7VALUE 7
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#define CFG_SPI_CS7VALUE 7
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#define CMD_SPI_SET_BAUDRATE 2
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#define CMD_SPI_GET_SYSTEMCLOCK 25
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#define CMD_SPI_SET_WRITECONTINUOUS 26
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/* device.platform_data for SSP controller devices */
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/* device.platform_data for SSP controller devices */
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struct bfin5xx_spi_master {
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struct bfin5xx_spi_master {
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u16 num_chipselect;
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u16 num_chipselect;
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