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phy: qcom-qusb2: Use HSTX_TRIM fused value as is 

Fix HSTX_TRIM tuning logic which instead of using fused value
as HSTX_TRIM, incorrectly performs bitwise OR operation with
existing default value.

Fixes: ca04d9d3e1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Manu Gautam 2018-10-16 12:52:06 +05:30 committed by Kishon Vijay Abraham I
parent 7243ec72b9
commit 6e34d358b2
1 changed files with 10 additions and 9 deletions
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19
drivers/phy/qualcomm/phy-qcom-qusb2.c
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@ -402,10 +402,10 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
/*
* Read efuse register having TUNE2/1 parameter's high nibble.
* If efuse register shows value as 0x0, or if we fail to find
* a valid efuse register settings, then use default value
* as 0xB for high nibble that we have already set while
* configuring phy.
* If efuse register shows value as 0x0 (indicating value is not
* fused), or if we fail to find a valid efuse register setting,
* then use default value for high nibble that we have already
* set while configuring the phy.
*/
val = nvmem_cell_read(qphy->cell, NULL);
if (IS_ERR(val) || !val[0]) {
@ -415,12 +415,13 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
/* Fused TUNE1/2 value is the higher nibble only */
if (cfg->update_tune1_with_efuse)
qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
val[0] << 0x4);
qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
val[0] << HSTX_TRIM_SHIFT,
HSTX_TRIM_MASK);
else
qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
val[0] << 0x4);
qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
val[0] << HSTX_TRIM_SHIFT,
HSTX_TRIM_MASK);
}
static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)