m68knommu: use read/write IO access functions in ColdFire m532x setup code
Get rid of the use of local IO access macros and switch to using the standard read*/write* family of access functions for the ColdFire m532x setup code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer
parent
e4c2b9befe
commit
6d8a1393ec
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@ -15,10 +15,6 @@
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#include <asm/m53xxacr.h>
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#define MCF_REG32(x) (*(volatile unsigned long *)(x))
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#define MCF_REG16(x) (*(volatile unsigned short *)(x))
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#define MCF_REG08(x) (*(volatile unsigned char *)(x))
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#define MCFINT_VECBASE 64
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#define MCFINT_UART0 26 /* Interrupt number for UART0 */
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#define MCFINT_UART1 27 /* Interrupt number for UART1 */
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@ -38,7 +34,7 @@
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#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
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#define MCF_WTM_WCR MCF_REG16(0xFC098000)
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#define MCF_WTM_WCR 0xFC098000
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/*
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* Define the 532x SIM register set addresses.
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@ -181,13 +177,13 @@
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_CCM_CCR MCF_REG16(0xFC0A0004)
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#define MCF_CCM_RCON MCF_REG16(0xFC0A0008)
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#define MCF_CCM_CIR MCF_REG16(0xFC0A000A)
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#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010)
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#define MCF_CCM_CDR MCF_REG16(0xFC0A0012)
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#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014)
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#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016)
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#define MCF_CCM_CCR 0xFC0A0004
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#define MCF_CCM_RCON 0xFC0A0008
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#define MCF_CCM_CIR 0xFC0A000A
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#define MCF_CCM_MISCCR 0xFC0A0010
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#define MCF_CCM_CDR 0xFC0A0012
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#define MCF_CCM_UHCSR 0xFC0A0014
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#define MCF_CCM_UOCSR 0xFC0A0016
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/* Bit definitions and macros for MCF_CCM_CCR */
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#define MCF_CCM_CCR_RESERVED (0x0001)
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@ -256,27 +252,24 @@
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000)
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#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004)
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#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008)
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#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C)
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#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010)
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#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014)
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#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018)
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#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C)
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#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020)
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#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024)
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#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028)
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#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C)
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#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030)
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#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034)
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#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038)
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#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C)
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#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040)
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#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044)
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#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
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#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
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#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
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#define MCF_FBCS0_CSAR 0xFC008000
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#define MCF_FBCS0_CSMR 0xFC008004
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#define MCF_FBCS0_CSCR 0xFC008008
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#define MCF_FBCS1_CSAR 0xFC00800C
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#define MCF_FBCS1_CSMR 0xFC008010
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#define MCF_FBCS1_CSCR 0xFC008014
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#define MCF_FBCS2_CSAR 0xFC008018
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#define MCF_FBCS2_CSMR 0xFC00801C
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#define MCF_FBCS2_CSCR 0xFC008020
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#define MCF_FBCS3_CSAR 0xFC008024
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#define MCF_FBCS3_CSMR 0xFC008028
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#define MCF_FBCS3_CSCR 0xFC00802C
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#define MCF_FBCS4_CSAR 0xFC008030
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#define MCF_FBCS4_CSMR 0xFC008034
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#define MCF_FBCS4_CSCR 0xFC008038
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#define MCF_FBCS5_CSAR 0xFC00803C
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#define MCF_FBCS5_CSMR 0xFC008040
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#define MCF_FBCS5_CSCR 0xFC008044
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/* Bit definitions and macros for MCF_FBCS_CSAR */
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#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
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@ -1114,10 +1107,10 @@
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_PLL_PODR MCF_REG08(0xFC0C0000)
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#define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004)
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#define MCF_PLL_PMDR MCF_REG08(0xFC0C0008)
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#define MCF_PLL_PFDR MCF_REG08(0xFC0C000C)
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#define MCF_PLL_PODR 0xFC0C0000
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#define MCF_PLL_PLLCR 0xFC0C0004
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#define MCF_PLL_PMDR 0xFC0C0008
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#define MCF_PLL_PFDR 0xFC0C000C
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/* Bit definitions and macros for MCF_PLL_PODR */
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#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
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@ -1140,15 +1133,15 @@
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_SCM_MPR MCF_REG32(0xFC000000)
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#define MCF_SCM_PACRA MCF_REG32(0xFC000020)
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#define MCF_SCM_PACRB MCF_REG32(0xFC000024)
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#define MCF_SCM_PACRC MCF_REG32(0xFC000028)
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#define MCF_SCM_PACRD MCF_REG32(0xFC00002C)
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#define MCF_SCM_PACRE MCF_REG32(0xFC000040)
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#define MCF_SCM_PACRF MCF_REG32(0xFC000044)
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#define MCF_SCM_MPR 0xFC000000
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#define MCF_SCM_PACRA 0xFC000020
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#define MCF_SCM_PACRB 0xFC000024
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#define MCF_SCM_PACRC 0xFC000028
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#define MCF_SCM_PACRD 0xFC00002C
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#define MCF_SCM_PACRE 0xFC000040
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#define MCF_SCM_PACRF 0xFC000044
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#define MCF_SCM_BCR MCF_REG32(0xFC040024)
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#define MCF_SCM_BCR 0xFC040024
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/*********************************************************************
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*
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@ -1157,17 +1150,16 @@
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000)
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#define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004)
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#define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008)
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#define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C)
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#define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080)
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#define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100)
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#define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110)
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#define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114)
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#define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118)
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#define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C)
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#define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004))
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#define MCF_SDRAMC_SDMR 0xFC0B8000
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#define MCF_SDRAMC_SDCR 0xFC0B8004
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#define MCF_SDRAMC_SDCFG1 0xFC0B8008
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#define MCF_SDRAMC_SDCFG2 0xFC0B800C
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#define MCF_SDRAMC_LIMP_FIX 0xFC0B8080
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#define MCF_SDRAMC_SDDS 0xFC0B8100
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#define MCF_SDRAMC_SDCS0 0xFC0B8110
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#define MCF_SDRAMC_SDCS1 0xFC0B8114
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#define MCF_SDRAMC_SDCS2 0xFC0B8118
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#define MCF_SDRAMC_SDCS3 0xFC0B811C
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/* Bit definitions and macros for MCF_SDRAMC_SDMR */
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#define MCF_SDRAMC_SDMR_CMD (0x00010000)
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@ -304,7 +304,7 @@ asmlinkage void __init sysinit(void)
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void wtm_init(void)
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{
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/* Disable watchdog timer */
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MCF_WTM_WCR = 0;
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writew(0, MCF_WTM_WCR);
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}
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#define MCF_SCM_BCR_GBW (0x00000100)
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@ -313,19 +313,19 @@ void wtm_init(void)
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void scm_init(void)
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{
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/* All masters are trusted */
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MCF_SCM_MPR = 0x77777777;
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writel(0x77777777, MCF_SCM_MPR);
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/* Allow supervisor/user, read/write, and trusted/untrusted
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access to all slaves */
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MCF_SCM_PACRA = 0;
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MCF_SCM_PACRB = 0;
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MCF_SCM_PACRC = 0;
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MCF_SCM_PACRD = 0;
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MCF_SCM_PACRE = 0;
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MCF_SCM_PACRF = 0;
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writel(0, MCF_SCM_PACRA);
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writel(0, MCF_SCM_PACRB);
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writel(0, MCF_SCM_PACRC);
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writel(0, MCF_SCM_PACRD);
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writel(0, MCF_SCM_PACRE);
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writel(0, MCF_SCM_PACRF);
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/* Enable bursts */
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MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW);
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writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
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}
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@ -334,32 +334,32 @@ void fbcs_init(void)
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writeb(0x3E, MCFGPIO_PAR_CS);
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/* Latch chip select */
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MCF_FBCS1_CSAR = 0x10080000;
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writel(0x10080000, MCF_FBCS1_CSAR);
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MCF_FBCS1_CSCR = 0x002A3780;
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MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V);
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writel(0x002A3780, MCF_FBCS1_CSCR);
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writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
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/* Initialize latch to drive signals to inactive states */
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*((u16 *)(0x10080000)) = 0xFFFF;
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writew(0xffff, 0x10080000);
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/* External SRAM */
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MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS;
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MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
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| MCF_FBCS_CSCR_AA
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| MCF_FBCS_CSCR_SBM
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| MCF_FBCS_CSCR_WS(1));
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MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
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| MCF_FBCS_CSMR_V);
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writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
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writel(MCF_FBCS_CSCR_PS_16 |
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MCF_FBCS_CSCR_AA |
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MCF_FBCS_CSCR_SBM |
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MCF_FBCS_CSCR_WS(1),
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MCF_FBCS1_CSCR);
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writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
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/* Boot Flash connected to FBCS0 */
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MCF_FBCS0_CSAR = FLASH_ADDRESS;
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MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
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| MCF_FBCS_CSCR_BEM
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| MCF_FBCS_CSCR_AA
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| MCF_FBCS_CSCR_SBM
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| MCF_FBCS_CSCR_WS(7));
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MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
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| MCF_FBCS_CSMR_V);
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writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
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writel(MCF_FBCS_CSCR_PS_16 |
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MCF_FBCS_CSCR_BEM |
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MCF_FBCS_CSCR_AA |
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MCF_FBCS_CSCR_SBM |
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MCF_FBCS_CSCR_WS(7),
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MCF_FBCS0_CSCR);
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writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
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}
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void sdramc_init(void)
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@ -368,86 +368,86 @@ void sdramc_init(void)
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* Check to see if the SDRAM has already been initialized
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* by a run control tool
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*/
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if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
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if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
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/* SDRAM chip select initialization */
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/* Initialize SDRAM chip select */
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MCF_SDRAMC_SDCS0 = (0
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| MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
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| MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE));
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writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
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MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
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MCF_SDRAMC_SDCS0);
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/*
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* Basic configuration and initialization
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*/
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MCF_SDRAMC_SDCFG1 = (0
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| MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
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| MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
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| MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
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| MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
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| MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
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| MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
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| MCF_SDRAMC_SDCFG1_WTLAT(3));
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MCF_SDRAMC_SDCFG2 = (0
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| MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
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| MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
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| MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5))
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| MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1));
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writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
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MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
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MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
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MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
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MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
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MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
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MCF_SDRAMC_SDCFG1_WTLAT(3),
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MCF_SDRAMC_SDCFG1);
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writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
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MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
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MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
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MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
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MCF_SDRAMC_SDCFG2);
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/*
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* Precharge and enable write to SDMR
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*/
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MCF_SDRAMC_SDCR = (0
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| MCF_SDRAMC_SDCR_MODE_EN
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| MCF_SDRAMC_SDCR_CKE
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| MCF_SDRAMC_SDCR_DDR
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| MCF_SDRAMC_SDCR_MUX(1)
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| MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
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| MCF_SDRAMC_SDCR_PS_16
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| MCF_SDRAMC_SDCR_IPALL);
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writel(MCF_SDRAMC_SDCR_MODE_EN |
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MCF_SDRAMC_SDCR_CKE |
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MCF_SDRAMC_SDCR_DDR |
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MCF_SDRAMC_SDCR_MUX(1) |
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MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
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MCF_SDRAMC_SDCR_PS_16 |
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MCF_SDRAMC_SDCR_IPALL,
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MCF_SDRAMC_SDCR);
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/*
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* Write extended mode register
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*/
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MCF_SDRAMC_SDMR = (0
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| MCF_SDRAMC_SDMR_BNKAD_LEMR
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| MCF_SDRAMC_SDMR_AD(0x0)
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| MCF_SDRAMC_SDMR_CMD);
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writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
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MCF_SDRAMC_SDMR_AD(0x0) |
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MCF_SDRAMC_SDMR_CMD,
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MCF_SDRAMC_SDMR);
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/*
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* Write mode register and reset DLL
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*/
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MCF_SDRAMC_SDMR = (0
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| MCF_SDRAMC_SDMR_BNKAD_LMR
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| MCF_SDRAMC_SDMR_AD(0x163)
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| MCF_SDRAMC_SDMR_CMD);
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writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
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MCF_SDRAMC_SDMR_AD(0x163) |
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MCF_SDRAMC_SDMR_CMD,
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MCF_SDRAMC_SDMR);
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/*
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* Execute a PALL command
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*/
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MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
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writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
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||||
|
||||
/*
|
||||
* Perform two REF cycles
|
||||
*/
|
||||
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
|
||||
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
|
||||
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
|
||||
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
|
||||
|
||||
/*
|
||||
* Write mode register and clear reset DLL
|
||||
*/
|
||||
MCF_SDRAMC_SDMR = (0
|
||||
| MCF_SDRAMC_SDMR_BNKAD_LMR
|
||||
| MCF_SDRAMC_SDMR_AD(0x063)
|
||||
| MCF_SDRAMC_SDMR_CMD);
|
||||
writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
|
||||
MCF_SDRAMC_SDMR_AD(0x063) |
|
||||
MCF_SDRAMC_SDMR_CMD,
|
||||
MCF_SDRAMC_SDMR);
|
||||
|
||||
/*
|
||||
* Enable auto refresh and lock SDMR
|
||||
*/
|
||||
MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
|
||||
MCF_SDRAMC_SDCR |= (0
|
||||
| MCF_SDRAMC_SDCR_REF
|
||||
| MCF_SDRAMC_SDCR_DQS_OE(0xC));
|
||||
writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
|
||||
MCF_SDRAMC_SDCR);
|
||||
writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
|
||||
MCF_SDRAMC_SDCR);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -475,7 +475,7 @@ int clock_pll(int fsys, int flags)
|
|||
|
||||
if (fsys == 0) {
|
||||
/* Return current PLL output */
|
||||
mfd = MCF_PLL_PFDR;
|
||||
mfd = readb(MCF_PLL_PFDR);
|
||||
|
||||
return (fref * mfd / (BUSDIV * 4));
|
||||
}
|
||||
|
|
@ -501,9 +501,10 @@ int clock_pll(int fsys, int flags)
|
|||
* If it has then the SDRAM needs to be put into self refresh
|
||||
* mode before reprogramming the PLL.
|
||||
*/
|
||||
if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
|
||||
if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
|
||||
/* Put SDRAM into self refresh mode */
|
||||
MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
|
||||
writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
|
||||
MCF_SDRAMC_SDCR);
|
||||
|
||||
/*
|
||||
* Initialize the PLL to generate the new system clock frequency.
|
||||
|
|
@ -514,11 +515,10 @@ int clock_pll(int fsys, int flags)
|
|||
clock_limp(DEFAULT_LPD);
|
||||
|
||||
/* Reprogram PLL for desired fsys */
|
||||
MCF_PLL_PODR = (0
|
||||
| MCF_PLL_PODR_CPUDIV(BUSDIV/3)
|
||||
| MCF_PLL_PODR_BUSDIV(BUSDIV));
|
||||
writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
|
||||
MCF_PLL_PODR);
|
||||
|
||||
MCF_PLL_PFDR = mfd;
|
||||
writeb(mfd, MCF_PLL_PFDR);
|
||||
|
||||
/* Exit LIMP mode */
|
||||
clock_exit_limp();
|
||||
|
|
@ -526,12 +526,13 @@ int clock_pll(int fsys, int flags)
|
|||
/*
|
||||
* Return the SDRAM to normal operation if it is in use.
|
||||
*/
|
||||
if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
|
||||
if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
|
||||
/* Exit self refresh mode */
|
||||
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
|
||||
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
|
||||
MCF_SDRAMC_SDCR);
|
||||
|
||||
/* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
|
||||
MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH;
|
||||
writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
|
||||
|
||||
/* wait for DQS logic to relock */
|
||||
for (i = 0; i < 0x200; i++)
|
||||
|
|
@ -552,14 +553,12 @@ int clock_limp(int div)
|
|||
|
||||
/* Save of the current value of the SSIDIV so we don't
|
||||
overwrite the value*/
|
||||
temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF));
|
||||
temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
|
||||
|
||||
/* Apply the divider to the system clock */
|
||||
MCF_CCM_CDR = ( 0
|
||||
| MCF_CCM_CDR_LPDIV(div)
|
||||
| MCF_CCM_CDR_SSIDIV(temp));
|
||||
writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
|
||||
|
||||
MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
|
||||
writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
|
||||
|
||||
return (FREF/(3*(1 << div)));
|
||||
}
|
||||
|
|
@ -569,10 +568,10 @@ int clock_exit_limp(void)
|
|||
int fout;
|
||||
|
||||
/* Exit LIMP mode */
|
||||
MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP);
|
||||
writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
|
||||
|
||||
/* Wait for PLL to lock */
|
||||
while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK))
|
||||
while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
|
||||
;
|
||||
|
||||
fout = get_sys_clock();
|
||||
|
|
@ -585,10 +584,10 @@ int get_sys_clock(void)
|
|||
int divider;
|
||||
|
||||
/* Test to see if device is in LIMP mode */
|
||||
if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) {
|
||||
divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF);
|
||||
if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
|
||||
divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
|
||||
return (FREF/(2 << divider));
|
||||
}
|
||||
else
|
||||
return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4));
|
||||
return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue