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omap3isp: Set cam_mclk rate directly 

Now that the cam_mclk rate changes are back-propagated to dpll4_m5_ck we
can set the cam_mclk rate directly instead of manually setting the rate
of the parent clock.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Sakari Ailus <sakari.ailus@iki.fi>
Tested-by: Sakari Ailus <sakari.ailus@iki.fi>
This commit is contained in:
Laurent Pinchart 2012-11-10 12:06:25 +01:00
parent 7b2e127759
commit 6d1aa02f10
2 changed files with 5 additions and 21 deletions
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18
drivers/media/platform/omap3isp/isp.c
View File

@ -1338,28 +1338,15 @@ static int isp_enable_clocks(struct isp_device *isp)
{
int r;
unsigned long rate;
int divisor;
/*
* cam_mclk clock chain:
* dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk
*
* In OMAP3630 dpll4_m5x2 != 2 x dpll4_m5 but both are
* set to the same value. Hence the rate set for dpll4_m5
* has to be twice of what is set on OMAP3430 to get
* the required value for cam_mclk
*/
divisor = isp->revision == ISP_REVISION_15_0 ? 1 : 2;
r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
if (r) {
dev_err(isp->dev, "failed to enable cam_ick clock\n");
goto out_clk_enable_ick;
}
r = clk_set_rate(isp->clock[ISP_CLK_DPLL4_M5_CK],
CM_CAM_MCLK_HZ/divisor);
r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
if (r) {
dev_err(isp->dev, "clk_set_rate for dpll4_m5_ck failed\n");
dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
goto out_clk_enable_mclk;
}
r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
@ -1401,7 +1388,6 @@ static void isp_disable_clocks(struct isp_device *isp)
static const char *isp_clocks[] = {
"cam_ick",
"cam_mclk",
"dpll4_m5_ck",
"csi2_96m_fck",
"l3_ick",
};

8
drivers/media/platform/omap3isp/isp.h
View File

@ -147,7 +147,6 @@ struct isp_platform_callback {
* @ref_count: Reference count for handling multiple ISP requests.
* @cam_ick: Pointer to camera interface clock structure.
* @cam_mclk: Pointer to camera functional clock structure.
* @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
* @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
* @l3_ick: Pointer to OMAP3 L3 bus interface clock.
* @irq: Currently attached ISP ISR callbacks information structure.
@ -189,10 +188,9 @@ struct isp_device {
u32 xclk_divisor[2]; /* Two clocks, a and b. */
#define ISP_CLK_CAM_ICK 0
#define ISP_CLK_CAM_MCLK 1
#define ISP_CLK_DPLL4_M5_CK 2
#define ISP_CLK_CSI2_FCK 3
#define ISP_CLK_L3_ICK 4
struct clk *clock[5];
#define ISP_CLK_CSI2_FCK 2
#define ISP_CLK_L3_ICK 3
struct clk *clock[4];
/* ISP modules */
struct ispstat isp_af;