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ARM: tegra: convert device tree files to use IRQ defines 

Use the GIC and standard IRQ binding defines in all IRQ specifiers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Stephen Warren 2013-02-13 12:51:51 -07:00
parent 3325f1bcd0
commit 6cecf916b9
16 changed files with 260 additions and 249 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/tegra114-dalmore.dts
View File

@ -748,7 +748,7 @@
compatible = "ti,tps65090"; compatible = "ti,tps65090";
reg = <0x48>; reg = <0x48>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <72 0x04>; /* gpio PJ0 */ interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
vsys1-supply = <&vdd_ac_bat_reg>; vsys1-supply = <&vdd_ac_bat_reg>;
vsys2-supply = <&vdd_ac_bat_reg>; vsys2-supply = <&vdd_ac_bat_reg>;

151
arch/arm/boot/dts/tegra114.dtsi
View File

@ -1,4 +1,5 @@
#include <dt-bindings/gpio/tegra-gpio.h> #include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi" #include "skeleton.dtsi"
@ -21,18 +22,19 @@
<0x50042000 0x1000>, <0x50042000 0x1000>,
<0x50044000 0x2000>, <0x50044000 0x2000>,
<0x50046000 0x2000>; <0x50046000 0x2000>;
interrupts = <1 9 0xf04>; interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
timer@60005000 { timer@60005000 {
compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>; reg = <0x60005000 0x400>;
interrupts = <0 0 0x04 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0 1 0x04 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0 41 0x04 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0 42 0x04 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0 121 0x04 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0 122 0x04>; <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 5>; clocks = <&tegra_car 5>;
}; };
@ -45,38 +47,38 @@
apbdma: dma { apbdma: dma {
compatible = "nvidia,tegra114-apbdma"; compatible = "nvidia,tegra114-apbdma";
reg = <0x6000a000 0x1400>; reg = <0x6000a000 0x1400>;
interrupts = <0 104 0x04 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0 105 0x04 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0 106 0x04 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0 107 0x04 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0 108 0x04 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0 109 0x04 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0 110 0x04 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0 111 0x04 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0 112 0x04 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0 113 0x04 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0 114 0x04 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0 115 0x04 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0 116 0x04 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0 117 0x04 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0 118 0x04 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0 119 0x04 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0 128 0x04 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0 129 0x04 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
0 130 0x04 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
0 131 0x04 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0 132 0x04 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
0 133 0x04 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
0 134 0x04 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0 135 0x04 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
0 136 0x04 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0 137 0x04 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0 138 0x04 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0 139 0x04 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
0 140 0x04 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0 141 0x04 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
0 142 0x04 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0 143 0x04>; <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 34>; clocks = <&tegra_car 34>;
}; };
@ -88,14 +90,14 @@
gpio: gpio { gpio: gpio {
compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>; reg = <0x6000d000 0x1000>;
interrupts = <0 32 0x04 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0 33 0x04 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0 34 0x04 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0 35 0x04 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0 55 0x04 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0 87 0x04 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0 89 0x04 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0 125 0x04>; <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
@ -120,7 +122,7 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>; reg = <0x70006000 0x40>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 36 0x04>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>; nvidia,dma-request-selector = <&apbdma 8>;
status = "disabled"; status = "disabled";
clocks = <&tegra_car 6>; clocks = <&tegra_car 6>;
@ -130,7 +132,7 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>; reg = <0x70006040 0x40>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 37 0x04>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>; nvidia,dma-request-selector = <&apbdma 9>;
status = "disabled"; status = "disabled";
clocks = <&tegra_car 192>; clocks = <&tegra_car 192>;
@ -140,7 +142,7 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>; reg = <0x70006200 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 46 0x04>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>; nvidia,dma-request-selector = <&apbdma 10>;
status = "disabled"; status = "disabled";
clocks = <&tegra_car 55>; clocks = <&tegra_car 55>;
@ -150,7 +152,7 @@
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>; reg = <0x70006300 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 90 0x04>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>; nvidia,dma-request-selector = <&apbdma 19>;
status = "disabled"; status = "disabled";
clocks = <&tegra_car 65>; clocks = <&tegra_car 65>;
@ -167,7 +169,7 @@
i2c@7000c000 { i2c@7000c000 {
compatible = "nvidia,tegra114-i2c"; compatible = "nvidia,tegra114-i2c";
reg = <0x7000c000 0x100>; reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 12>; clocks = <&tegra_car 12>;
@ -178,7 +180,7 @@
i2c@7000c400 { i2c@7000c400 {
compatible = "nvidia,tegra114-i2c"; compatible = "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>; reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 54>; clocks = <&tegra_car 54>;
@ -189,7 +191,7 @@
i2c@7000c500 { i2c@7000c500 {
compatible = "nvidia,tegra114-i2c"; compatible = "nvidia,tegra114-i2c";
reg = <0x7000c500 0x100>; reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 67>; clocks = <&tegra_car 67>;
@ -200,7 +202,7 @@
i2c@7000c700 { i2c@7000c700 {
compatible = "nvidia,tegra114-i2c"; compatible = "nvidia,tegra114-i2c";
reg = <0x7000c700 0x100>; reg = <0x7000c700 0x100>;
interrupts = <0 120 0x04>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 103>; clocks = <&tegra_car 103>;
@ -211,7 +213,7 @@
i2c@7000d000 { i2c@7000d000 {
compatible = "nvidia,tegra114-i2c"; compatible = "nvidia,tegra114-i2c";
reg = <0x7000d000 0x100>; reg = <0x7000d000 0x100>;
interrupts = <0 53 0x04>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 47>; clocks = <&tegra_car 47>;
@ -222,7 +224,7 @@
spi@7000d400 { spi@7000d400 {
compatible = "nvidia,tegra114-spi"; compatible = "nvidia,tegra114-spi";
reg = <0x7000d400 0x200>; reg = <0x7000d400 0x200>;
interrupts = <0 59 0x04>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 15>; nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -234,7 +236,7 @@
spi@7000d600 { spi@7000d600 {
compatible = "nvidia,tegra114-spi"; compatible = "nvidia,tegra114-spi";
reg = <0x7000d600 0x200>; reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 16>; nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -246,7 +248,7 @@
spi@7000d800 { spi@7000d800 {
compatible = "nvidia,tegra114-spi"; compatible = "nvidia,tegra114-spi";
reg = <0x7000d800 0x200>; reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 17>; nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -258,7 +260,7 @@
spi@7000da00 { spi@7000da00 {
compatible = "nvidia,tegra114-spi"; compatible = "nvidia,tegra114-spi";
reg = <0x7000da00 0x200>; reg = <0x7000da00 0x200>;
interrupts = <0 93 0x04>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 18>; nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -270,7 +272,7 @@
spi@7000dc00 { spi@7000dc00 {
compatible = "nvidia,tegra114-spi"; compatible = "nvidia,tegra114-spi";
reg = <0x7000dc00 0x200>; reg = <0x7000dc00 0x200>;
interrupts = <0 94 0x04>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 27>; nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -282,7 +284,7 @@
spi@7000de00 { spi@7000de00 {
compatible = "nvidia,tegra114-spi"; compatible = "nvidia,tegra114-spi";
reg = <0x7000de00 0x200>; reg = <0x7000de00 0x200>;
interrupts = <0 79 0x04>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 28>; nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -294,14 +296,14 @@
rtc { rtc {
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>; reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 4>; clocks = <&tegra_car 4>;
}; };
kbc { kbc {
compatible = "nvidia,tegra114-kbc"; compatible = "nvidia,tegra114-kbc";
reg = <0x7000e200 0x100>; reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 36>; clocks = <&tegra_car 36>;
status = "disabled"; status = "disabled";
}; };
@ -327,7 +329,7 @@
sdhci@78000000 { sdhci@78000000 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000000 0x200>; reg = <0x78000000 0x200>;
interrupts = <0 14 0x04>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 14>; clocks = <&tegra_car 14>;
status = "disable"; status = "disable";
}; };
@ -335,7 +337,7 @@
sdhci@78000200 { sdhci@78000200 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000200 0x200>; reg = <0x78000200 0x200>;
interrupts = <0 15 0x04>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 9>; clocks = <&tegra_car 9>;
status = "disable"; status = "disable";
}; };
@ -343,7 +345,7 @@
sdhci@78000400 { sdhci@78000400 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000400 0x200>; reg = <0x78000400 0x200>;
interrupts = <0 19 0x04>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 69>; clocks = <&tegra_car 69>;
status = "disable"; status = "disable";
}; };
@ -351,7 +353,7 @@
sdhci@78000600 { sdhci@78000600 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000600 0x200>; reg = <0x78000600 0x200>;
interrupts = <0 31 0x04>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 15>; clocks = <&tegra_car 15>;
status = "disable"; status = "disable";
}; };
@ -387,9 +389,14 @@
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>, interrupts =
<1 14 0xf08>, <GIC_PPI 13
<1 11 0xf08>, (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 10 0xf08>; <GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
}; };
}; };

2
arch/arm/boot/dts/tegra20-colibri-512.dtsi
View File

@ -218,7 +218,7 @@
pmic: tps6586x@34 { pmic: tps6586x@34 {
compatible = "ti,tps6586x"; compatible = "ti,tps6586x";
reg = <0x34>; reg = <0x34>;
interrupts = <0 86 0x4>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller; ti,system-power-controller;

4
arch/arm/boot/dts/tegra20-harmony.dts
View File

@ -263,7 +263,7 @@
compatible = "wlf,wm8903"; compatible = "wlf,wm8903";
reg = <0x1a>; reg = <0x1a>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 3) 0x04>; interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
@ -291,7 +291,7 @@
pmic: tps6586x@34 { pmic: tps6586x@34 {
compatible = "ti,tps6586x"; compatible = "ti,tps6586x";
reg = <0x34>; reg = <0x34>;
interrupts = <0 86 0x4>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller; ti,system-power-controller;

2
arch/arm/boot/dts/tegra20-medcom-wide.dts
View File

@ -15,7 +15,7 @@
compatible = "wlf,wm8903"; compatible = "wlf,wm8903";
reg = <0x1a>; reg = <0x1a>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 3) 0x04>; interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;

4
arch/arm/boot/dts/tegra20-paz00.dts
View File

@ -271,7 +271,7 @@
nvec { nvec {
compatible = "nvidia,nvec"; compatible = "nvidia,nvec";
reg = <0x7000c500 0x100>; reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clock-frequency = <80000>; clock-frequency = <80000>;
@ -288,7 +288,7 @@
pmic: tps6586x@34 { pmic: tps6586x@34 {
compatible = "ti,tps6586x"; compatible = "ti,tps6586x";
reg = <0x34>; reg = <0x34>;
interrupts = <0 86 0x4>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;

2
arch/arm/boot/dts/tegra20-plutux.dts
View File

@ -17,7 +17,7 @@
compatible = "wlf,wm8903"; compatible = "wlf,wm8903";
reg = <0x1a>; reg = <0x1a>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 3) 0x04>; interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;

10
arch/arm/boot/dts/tegra20-seaboard.dts
View File

@ -314,7 +314,7 @@
compatible = "wlf,wm8903"; compatible = "wlf,wm8903";
reg = <0x1a>; reg = <0x1a>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 3) 0x04>; interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
@ -329,14 +329,14 @@
compatible = "isil,isl29018"; compatible = "isil,isl29018";
reg = <0x44>; reg = <0x44>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(Z, 2) 0x04>; interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
}; };
gyrometer@68 { gyrometer@68 {
compatible = "invn,mpu3050"; compatible = "invn,mpu3050";
reg = <0x68>; reg = <0x68>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(Z, 4) 0x04>; interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
}; };
}; };
@ -389,7 +389,7 @@
pmic: tps6586x@34 { pmic: tps6586x@34 {
compatible = "ti,tps6586x"; compatible = "ti,tps6586x";
reg = <0x34>; reg = <0x34>;
interrupts = <0 86 0x4>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller; ti,system-power-controller;
@ -512,7 +512,7 @@
compatible = "ak,ak8975"; compatible = "ak,ak8975";
reg = <0xc>; reg = <0xc>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(N, 5) 0x04>; interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
}; };
}; };

2
arch/arm/boot/dts/tegra20-tamonten.dtsi
View File

@ -322,7 +322,7 @@
pmic: tps6586x@34 { pmic: tps6586x@34 {
compatible = "ti,tps6586x"; compatible = "ti,tps6586x";
reg = <0x34>; reg = <0x34>;
interrupts = <0 86 0x4>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller; ti,system-power-controller;

2
arch/arm/boot/dts/tegra20-tec.dts
View File

@ -17,7 +17,7 @@
compatible = "wlf,wm8903"; compatible = "wlf,wm8903";
reg = <0x1a>; reg = <0x1a>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 3) 0x04>; interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;

6
arch/arm/boot/dts/tegra20-ventana.dts
View File

@ -311,7 +311,7 @@
compatible = "wlf,wm8903"; compatible = "wlf,wm8903";
reg = <0x1a>; reg = <0x1a>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 3) 0x04>; interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
@ -326,7 +326,7 @@
compatible = "isil,isl29018"; compatible = "isil,isl29018";
reg = <0x44>; reg = <0x44>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(Z, 2) 0x04>; interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
}; };
}; };
@ -372,7 +372,7 @@
pmic: tps6586x@34 { pmic: tps6586x@34 {
compatible = "ti,tps6586x"; compatible = "ti,tps6586x";
reg = <0x34>; reg = <0x34>;
interrupts = <0 86 0x4>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller; ti,system-power-controller;

2
arch/arm/boot/dts/tegra20-whistler.dts
View File

@ -282,7 +282,7 @@
max8907@3c { max8907@3c {
compatible = "maxim,max8907"; compatible = "maxim,max8907";
reg = <0x3c>; reg = <0x3c>;
interrupts = <0 86 0x4>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
maxim,system-power-controller; maxim,system-power-controller;

138
arch/arm/boot/dts/tegra20.dtsi
View File

@ -1,4 +1,5 @@
#include <dt-bindings/gpio/tegra-gpio.h> #include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi" #include "skeleton.dtsi"
@ -17,8 +18,8 @@
host1x { host1x {
compatible = "nvidia,tegra20-host1x", "simple-bus"; compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>; reg = <0x50000000 0x00024000>;
interrupts = <0 65 0x04 /* mpcore syncpt */ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
0 67 0x04>; /* mpcore general */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car 28>; clocks = <&tegra_car 28>;
#address-cells = <1>; #address-cells = <1>;
@ -29,35 +30,35 @@
mpe { mpe {
compatible = "nvidia,tegra20-mpe"; compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>; reg = <0x54040000 0x00040000>;
interrupts = <0 68 0x04>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 60>; clocks = <&tegra_car 60>;
}; };
vi { vi {
compatible = "nvidia,tegra20-vi"; compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>; reg = <0x54080000 0x00040000>;
interrupts = <0 69 0x04>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 100>; clocks = <&tegra_car 100>;
}; };
epp { epp {
compatible = "nvidia,tegra20-epp"; compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>; reg = <0x540c0000 0x00040000>;
interrupts = <0 70 0x04>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 19>; clocks = <&tegra_car 19>;
}; };
isp { isp {
compatible = "nvidia,tegra20-isp"; compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>; reg = <0x54100000 0x00040000>;
interrupts = <0 71 0x04>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 23>; clocks = <&tegra_car 23>;
}; };
gr2d { gr2d {
compatible = "nvidia,tegra20-gr2d"; compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>; reg = <0x54140000 0x00040000>;
interrupts = <0 72 0x04>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 21>; clocks = <&tegra_car 21>;
}; };
@ -70,7 +71,7 @@
dc@54200000 { dc@54200000 {
compatible = "nvidia,tegra20-dc"; compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>; reg = <0x54200000 0x00040000>;
interrupts = <0 73 0x04>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 27>, <&tegra_car 121>; clocks = <&tegra_car 27>, <&tegra_car 121>;
clock-names = "disp1", "parent"; clock-names = "disp1", "parent";
@ -82,7 +83,7 @@
dc@54240000 { dc@54240000 {
compatible = "nvidia,tegra20-dc"; compatible = "nvidia,tegra20-dc";
reg = <0x54240000 0x00040000>; reg = <0x54240000 0x00040000>;
interrupts = <0 74 0x04>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 26>, <&tegra_car 121>; clocks = <&tegra_car 26>, <&tegra_car 121>;
clock-names = "disp2", "parent"; clock-names = "disp2", "parent";
@ -94,7 +95,7 @@
hdmi { hdmi {
compatible = "nvidia,tegra20-hdmi"; compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>; reg = <0x54280000 0x00040000>;
interrupts = <0 75 0x04>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 51>, <&tegra_car 117>; clocks = <&tegra_car 51>, <&tegra_car 117>;
clock-names = "hdmi", "parent"; clock-names = "hdmi", "parent";
status = "disabled"; status = "disabled";
@ -103,7 +104,7 @@
tvo { tvo {
compatible = "nvidia,tegra20-tvo"; compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>; reg = <0x542c0000 0x00040000>;
interrupts = <0 76 0x04>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 102>; clocks = <&tegra_car 102>;
status = "disabled"; status = "disabled";
}; };
@ -119,7 +120,8 @@
timer@50004600 { timer@50004600 {
compatible = "arm,cortex-a9-twd-timer"; compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>; reg = <0x50040600 0x20>;
interrupts = <1 13 0x304>; interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&tegra_car 132>; clocks = <&tegra_car 132>;
}; };
@ -143,10 +145,10 @@
timer@60005000 { timer@60005000 {
compatible = "nvidia,tegra20-timer"; compatible = "nvidia,tegra20-timer";
reg = <0x60005000 0x60>; reg = <0x60005000 0x60>;
interrupts = <0 0 0x04 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0 1 0x04 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0 41 0x04 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0 42 0x04>; <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 5>; clocks = <&tegra_car 5>;
}; };
@ -159,22 +161,22 @@
apbdma: dma { apbdma: dma {
compatible = "nvidia,tegra20-apbdma"; compatible = "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1200>; reg = <0x6000a000 0x1200>;
interrupts = <0 104 0x04 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0 105 0x04 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0 106 0x04 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0 107 0x04 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0 108 0x04 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0 109 0x04 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0 110 0x04 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0 111 0x04 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0 112 0x04 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0 113 0x04 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0 114 0x04 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0 115 0x04 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0 116 0x04 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0 117 0x04 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0 118 0x04 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0 119 0x04>; <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 34>; clocks = <&tegra_car 34>;
}; };
@ -186,13 +188,13 @@
gpio: gpio { gpio: gpio {
compatible = "nvidia,tegra20-gpio"; compatible = "nvidia,tegra20-gpio";
reg = <0x6000d000 0x1000>; reg = <0x6000d000 0x1000>;
interrupts = <0 32 0x04 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0 33 0x04 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0 34 0x04 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0 35 0x04 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0 55 0x04 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0 87 0x04 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0 89 0x04>; <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
@ -215,7 +217,7 @@
tegra_ac97: ac97 { tegra_ac97: ac97 {
compatible = "nvidia,tegra20-ac97"; compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>; reg = <0x70002000 0x200>;
interrupts = <0 81 0x04>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 12>; nvidia,dma-request-selector = <&apbdma 12>;
clocks = <&tegra_car 3>; clocks = <&tegra_car 3>;
status = "disabled"; status = "disabled";
@ -224,7 +226,7 @@
tegra_i2s1: i2s@70002800 { tegra_i2s1: i2s@70002800 {
compatible = "nvidia,tegra20-i2s"; compatible = "nvidia,tegra20-i2s";
reg = <0x70002800 0x200>; reg = <0x70002800 0x200>;
interrupts = <0 13 0x04>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 2>; nvidia,dma-request-selector = <&apbdma 2>;
clocks = <&tegra_car 11>; clocks = <&tegra_car 11>;
status = "disabled"; status = "disabled";
@ -233,7 +235,7 @@
tegra_i2s2: i2s@70002a00 { tegra_i2s2: i2s@70002a00 {
compatible = "nvidia,tegra20-i2s"; compatible = "nvidia,tegra20-i2s";
reg = <0x70002a00 0x200>; reg = <0x70002a00 0x200>;
interrupts = <0 3 0x04>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>; nvidia,dma-request-selector = <&apbdma 1>;
clocks = <&tegra_car 18>; clocks = <&tegra_car 18>;
status = "disabled"; status = "disabled";
@ -250,7 +252,7 @@
compatible = "nvidia,tegra20-uart"; compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>; reg = <0x70006000 0x40>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 36 0x04>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>; nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>; clocks = <&tegra_car 6>;
status = "disabled"; status = "disabled";
@ -260,7 +262,7 @@
compatible = "nvidia,tegra20-uart"; compatible = "nvidia,tegra20-uart";
reg = <0x70006040 0x40>; reg = <0x70006040 0x40>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 37 0x04>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>; nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 96>; clocks = <&tegra_car 96>;
status = "disabled"; status = "disabled";
@ -270,7 +272,7 @@
compatible = "nvidia,tegra20-uart"; compatible = "nvidia,tegra20-uart";
reg = <0x70006200 0x100>; reg = <0x70006200 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 46 0x04>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>; nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>; clocks = <&tegra_car 55>;
status = "disabled"; status = "disabled";
@ -280,7 +282,7 @@
compatible = "nvidia,tegra20-uart"; compatible = "nvidia,tegra20-uart";
reg = <0x70006300 0x100>; reg = <0x70006300 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 90 0x04>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>; nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>; clocks = <&tegra_car 65>;
status = "disabled"; status = "disabled";
@ -290,7 +292,7 @@
compatible = "nvidia,tegra20-uart"; compatible = "nvidia,tegra20-uart";
reg = <0x70006400 0x100>; reg = <0x70006400 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 91 0x04>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 20>; nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>; clocks = <&tegra_car 66>;
status = "disabled"; status = "disabled";
@ -307,14 +309,14 @@
rtc { rtc {
compatible = "nvidia,tegra20-rtc"; compatible = "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>; reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 4>; clocks = <&tegra_car 4>;
}; };
i2c@7000c000 { i2c@7000c000 {
compatible = "nvidia,tegra20-i2c"; compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>; reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 124>; clocks = <&tegra_car 12>, <&tegra_car 124>;
@ -325,7 +327,7 @@
spi@7000c380 { spi@7000c380 {
compatible = "nvidia,tegra20-sflash"; compatible = "nvidia,tegra20-sflash";
reg = <0x7000c380 0x80>; reg = <0x7000c380 0x80>;
interrupts = <0 39 0x04>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 11>; nvidia,dma-request-selector = <&apbdma 11>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -336,7 +338,7 @@
i2c@7000c400 { i2c@7000c400 {
compatible = "nvidia,tegra20-i2c"; compatible = "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>; reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 54>, <&tegra_car 124>; clocks = <&tegra_car 54>, <&tegra_car 124>;
@ -347,7 +349,7 @@
i2c@7000c500 { i2c@7000c500 {
compatible = "nvidia,tegra20-i2c"; compatible = "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>; reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 67>, <&tegra_car 124>; clocks = <&tegra_car 67>, <&tegra_car 124>;
@ -358,7 +360,7 @@
i2c@7000d000 { i2c@7000d000 {
compatible = "nvidia,tegra20-i2c-dvc"; compatible = "nvidia,tegra20-i2c-dvc";
reg = <0x7000d000 0x200>; reg = <0x7000d000 0x200>;
interrupts = <0 53 0x04>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 47>, <&tegra_car 124>; clocks = <&tegra_car 47>, <&tegra_car 124>;
@ -369,7 +371,7 @@
spi@7000d400 { spi@7000d400 {
compatible = "nvidia,tegra20-slink"; compatible = "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>; reg = <0x7000d400 0x200>;
interrupts = <0 59 0x04>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 15>; nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -380,7 +382,7 @@
spi@7000d600 { spi@7000d600 {
compatible = "nvidia,tegra20-slink"; compatible = "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>; reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 16>; nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -391,7 +393,7 @@
spi@7000d800 { spi@7000d800 {
compatible = "nvidia,tegra20-slink"; compatible = "nvidia,tegra20-slink";
reg = <0x7000d800 0x200>; reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 17>; nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -402,7 +404,7 @@
spi@7000da00 { spi@7000da00 {
compatible = "nvidia,tegra20-slink"; compatible = "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>; reg = <0x7000da00 0x200>;
interrupts = <0 93 0x04>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 18>; nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -413,7 +415,7 @@
kbc { kbc {
compatible = "nvidia,tegra20-kbc"; compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>; reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 36>; clocks = <&tegra_car 36>;
status = "disabled"; status = "disabled";
}; };
@ -429,7 +431,7 @@
compatible = "nvidia,tegra20-mc"; compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024 reg = <0x7000f000 0x024
0x7000f03c 0x3c4>; 0x7000f03c 0x3c4>;
interrupts = <0 77 0x04>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
}; };
iommu { iommu {
@ -448,7 +450,7 @@
usb@c5000000 { usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci"; compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>; reg = <0xc5000000 0x4000>;
interrupts = <0 20 0x04>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi"; phy_type = "utmi";
nvidia,has-legacy-mode; nvidia,has-legacy-mode;
clocks = <&tegra_car 22>; clocks = <&tegra_car 22>;
@ -480,7 +482,7 @@
usb@c5004000 { usb@c5004000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci"; compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5004000 0x4000>; reg = <0xc5004000 0x4000>;
interrupts = <0 21 0x04>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "ulpi"; phy_type = "ulpi";
clocks = <&tegra_car 58>; clocks = <&tegra_car 58>;
nvidia,phy = <&phy2>; nvidia,phy = <&phy2>;
@ -501,7 +503,7 @@
usb@c5008000 { usb@c5008000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci"; compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5008000 0x4000>; reg = <0xc5008000 0x4000>;
interrupts = <0 97 0x04>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi"; phy_type = "utmi";
clocks = <&tegra_car 59>; clocks = <&tegra_car 59>;
nvidia,phy = <&phy3>; nvidia,phy = <&phy3>;
@ -530,7 +532,7 @@
sdhci@c8000000 { sdhci@c8000000 {
compatible = "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>; reg = <0xc8000000 0x200>;
interrupts = <0 14 0x04>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 14>; clocks = <&tegra_car 14>;
status = "disabled"; status = "disabled";
}; };
@ -538,7 +540,7 @@
sdhci@c8000200 { sdhci@c8000200 {
compatible = "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>; reg = <0xc8000200 0x200>;
interrupts = <0 15 0x04>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 9>; clocks = <&tegra_car 9>;
status = "disabled"; status = "disabled";
}; };
@ -546,7 +548,7 @@
sdhci@c8000400 { sdhci@c8000400 {
compatible = "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>; reg = <0xc8000400 0x200>;
interrupts = <0 19 0x04>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 69>; clocks = <&tegra_car 69>;
status = "disabled"; status = "disabled";
}; };
@ -554,7 +556,7 @@
sdhci@c8000600 { sdhci@c8000600 {
compatible = "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>; reg = <0xc8000600 0x200>;
interrupts = <0 31 0x04>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 15>; clocks = <&tegra_car 15>;
status = "disabled"; status = "disabled";
}; };
@ -578,7 +580,7 @@
pmu { pmu {
compatible = "arm,cortex-a9-pmu"; compatible = "arm,cortex-a9-pmu";
interrupts = <0 56 0x04 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0 57 0x04>; <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
}; };
}; };

2
arch/arm/boot/dts/tegra30-beaver.dts
View File

@ -133,7 +133,7 @@
compatible = "ti,tps65911"; compatible = "ti,tps65911";
reg = <0x2d>; reg = <0x2d>;
interrupts = <0 86 0x4>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;

6
arch/arm/boot/dts/tegra30-cardhu.dtsi
View File

@ -146,7 +146,7 @@
compatible = "isil,isl29028"; compatible = "isil,isl29028";
reg = <0x44>; reg = <0x44>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(L, 0) 0x04>; interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
}; };
}; };
@ -163,7 +163,7 @@
compatible = "wlf,wm8903"; compatible = "wlf,wm8903";
reg = <0x1a>; reg = <0x1a>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(W, 3) 0x04>; interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
@ -190,7 +190,7 @@
compatible = "ti,tps65911"; compatible = "ti,tps65911";
reg = <0x2d>; reg = <0x2d>;
interrupts = <0 86 0x4>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;

174
arch/arm/boot/dts/tegra30.dtsi
View File

@ -1,4 +1,5 @@
#include <dt-bindings/gpio/tegra-gpio.h> #include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi" #include "skeleton.dtsi"
@ -17,8 +18,8 @@
host1x { host1x {
compatible = "nvidia,tegra30-host1x", "simple-bus"; compatible = "nvidia,tegra30-host1x", "simple-bus";
reg = <0x50000000 0x00024000>; reg = <0x50000000 0x00024000>;
interrupts = <0 65 0x04 /* mpcore syncpt */ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
0 67 0x04>; /* mpcore general */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car 28>; clocks = <&tegra_car 28>;
#address-cells = <1>; #address-cells = <1>;
@ -29,35 +30,35 @@
mpe { mpe {
compatible = "nvidia,tegra30-mpe"; compatible = "nvidia,tegra30-mpe";
reg = <0x54040000 0x00040000>; reg = <0x54040000 0x00040000>;
interrupts = <0 68 0x04>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 60>; clocks = <&tegra_car 60>;
}; };
vi { vi {
compatible = "nvidia,tegra30-vi"; compatible = "nvidia,tegra30-vi";
reg = <0x54080000 0x00040000>; reg = <0x54080000 0x00040000>;
interrupts = <0 69 0x04>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 164>; clocks = <&tegra_car 164>;
}; };
epp { epp {
compatible = "nvidia,tegra30-epp"; compatible = "nvidia,tegra30-epp";
reg = <0x540c0000 0x00040000>; reg = <0x540c0000 0x00040000>;
interrupts = <0 70 0x04>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 19>; clocks = <&tegra_car 19>;
}; };
isp { isp {
compatible = "nvidia,tegra30-isp"; compatible = "nvidia,tegra30-isp";
reg = <0x54100000 0x00040000>; reg = <0x54100000 0x00040000>;
interrupts = <0 71 0x04>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 23>; clocks = <&tegra_car 23>;
}; };
gr2d { gr2d {
compatible = "nvidia,tegra30-gr2d"; compatible = "nvidia,tegra30-gr2d";
reg = <0x54140000 0x00040000>; reg = <0x54140000 0x00040000>;
interrupts = <0 72 0x04>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 21>; clocks = <&tegra_car 21>;
}; };
@ -71,7 +72,7 @@
dc@54200000 { dc@54200000 {
compatible = "nvidia,tegra30-dc"; compatible = "nvidia,tegra30-dc";
reg = <0x54200000 0x00040000>; reg = <0x54200000 0x00040000>;
interrupts = <0 73 0x04>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 27>, <&tegra_car 179>; clocks = <&tegra_car 27>, <&tegra_car 179>;
clock-names = "disp1", "parent"; clock-names = "disp1", "parent";
@ -83,7 +84,7 @@
dc@54240000 { dc@54240000 {
compatible = "nvidia,tegra30-dc"; compatible = "nvidia,tegra30-dc";
reg = <0x54240000 0x00040000>; reg = <0x54240000 0x00040000>;
interrupts = <0 74 0x04>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 26>, <&tegra_car 179>; clocks = <&tegra_car 26>, <&tegra_car 179>;
clock-names = "disp2", "parent"; clock-names = "disp2", "parent";
@ -95,7 +96,7 @@
hdmi { hdmi {
compatible = "nvidia,tegra30-hdmi"; compatible = "nvidia,tegra30-hdmi";
reg = <0x54280000 0x00040000>; reg = <0x54280000 0x00040000>;
interrupts = <0 75 0x04>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 51>, <&tegra_car 189>; clocks = <&tegra_car 51>, <&tegra_car 189>;
clock-names = "hdmi", "parent"; clock-names = "hdmi", "parent";
status = "disabled"; status = "disabled";
@ -104,7 +105,7 @@
tvo { tvo {
compatible = "nvidia,tegra30-tvo"; compatible = "nvidia,tegra30-tvo";
reg = <0x542c0000 0x00040000>; reg = <0x542c0000 0x00040000>;
interrupts = <0 76 0x04>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 169>; clocks = <&tegra_car 169>;
status = "disabled"; status = "disabled";
}; };
@ -120,7 +121,8 @@
timer@50004600 { timer@50004600 {
compatible = "arm,cortex-a9-twd-timer"; compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>; reg = <0x50040600 0x20>;
interrupts = <1 13 0xf04>; interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&tegra_car 214>; clocks = <&tegra_car 214>;
}; };
@ -144,12 +146,12 @@
timer@60005000 { timer@60005000 {
compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>; reg = <0x60005000 0x400>;
interrupts = <0 0 0x04 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0 1 0x04 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0 41 0x04 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0 42 0x04 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0 121 0x04 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0 122 0x04>; <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 5>; clocks = <&tegra_car 5>;
}; };
@ -162,38 +164,38 @@
apbdma: dma { apbdma: dma {
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1400>; reg = <0x6000a000 0x1400>;
interrupts = <0 104 0x04 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0 105 0x04 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0 106 0x04 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0 107 0x04 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0 108 0x04 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0 109 0x04 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0 110 0x04 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0 111 0x04 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0 112 0x04 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0 113 0x04 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0 114 0x04 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0 115 0x04 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0 116 0x04 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0 117 0x04 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0 118 0x04 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0 119 0x04 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0 128 0x04 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0 129 0x04 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
0 130 0x04 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
0 131 0x04 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0 132 0x04 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
0 133 0x04 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
0 134 0x04 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0 135 0x04 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
0 136 0x04 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0 137 0x04 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0 138 0x04 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0 139 0x04 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
0 140 0x04 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0 141 0x04 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
0 142 0x04 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0 143 0x04>; <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 34>; clocks = <&tegra_car 34>;
}; };
@ -205,14 +207,14 @@
gpio: gpio { gpio: gpio {
compatible = "nvidia,tegra30-gpio"; compatible = "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>; reg = <0x6000d000 0x1000>;
interrupts = <0 32 0x04 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0 33 0x04 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0 34 0x04 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0 35 0x04 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0 55 0x04 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0 87 0x04 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0 89 0x04 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0 125 0x04>; <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
@ -237,7 +239,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>; reg = <0x70006000 0x40>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 36 0x04>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 8>; nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>; clocks = <&tegra_car 6>;
status = "disabled"; status = "disabled";
@ -247,7 +249,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>; reg = <0x70006040 0x40>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 37 0x04>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 9>; nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 160>; clocks = <&tegra_car 160>;
status = "disabled"; status = "disabled";
@ -257,7 +259,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>; reg = <0x70006200 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 46 0x04>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 10>; nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>; clocks = <&tegra_car 55>;
status = "disabled"; status = "disabled";
@ -267,7 +269,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>; reg = <0x70006300 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 90 0x04>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 19>; nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>; clocks = <&tegra_car 65>;
status = "disabled"; status = "disabled";
@ -277,7 +279,7 @@
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006400 0x100>; reg = <0x70006400 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 91 0x04>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 20>; nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>; clocks = <&tegra_car 66>;
status = "disabled"; status = "disabled";
@ -294,14 +296,14 @@
rtc { rtc {
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>; reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 4>; clocks = <&tegra_car 4>;
}; };
i2c@7000c000 { i2c@7000c000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>; reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 182>; clocks = <&tegra_car 12>, <&tegra_car 182>;
@ -312,7 +314,7 @@
i2c@7000c400 { i2c@7000c400 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>; reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 54>, <&tegra_car 182>; clocks = <&tegra_car 54>, <&tegra_car 182>;
@ -323,7 +325,7 @@
i2c@7000c500 { i2c@7000c500 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>; reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 67>, <&tegra_car 182>; clocks = <&tegra_car 67>, <&tegra_car 182>;
@ -334,7 +336,7 @@
i2c@7000c700 { i2c@7000c700 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000c700 0x100>; reg = <0x7000c700 0x100>;
interrupts = <0 120 0x04>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 103>, <&tegra_car 182>; clocks = <&tegra_car 103>, <&tegra_car 182>;
@ -345,7 +347,7 @@
i2c@7000d000 { i2c@7000d000 {
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
reg = <0x7000d000 0x100>; reg = <0x7000d000 0x100>;
interrupts = <0 53 0x04>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&tegra_car 47>, <&tegra_car 182>; clocks = <&tegra_car 47>, <&tegra_car 182>;
@ -356,7 +358,7 @@
spi@7000d400 { spi@7000d400 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>; reg = <0x7000d400 0x200>;
interrupts = <0 59 0x04>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 15>; nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -367,7 +369,7 @@
spi@7000d600 { spi@7000d600 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>; reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 16>; nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -378,7 +380,7 @@
spi@7000d800 { spi@7000d800 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000d800 0x200>; reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 17>; nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -389,7 +391,7 @@
spi@7000da00 { spi@7000da00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>; reg = <0x7000da00 0x200>;
interrupts = <0 93 0x04>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 18>; nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -400,7 +402,7 @@
spi@7000dc00 { spi@7000dc00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000dc00 0x200>; reg = <0x7000dc00 0x200>;
interrupts = <0 94 0x04>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 27>; nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -411,7 +413,7 @@
spi@7000de00 { spi@7000de00 {
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
reg = <0x7000de00 0x200>; reg = <0x7000de00 0x200>;
interrupts = <0 79 0x04>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 28>; nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -422,7 +424,7 @@
kbc { kbc {
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>; reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 36>; clocks = <&tegra_car 36>;
status = "disabled"; status = "disabled";
}; };
@ -440,7 +442,7 @@
0x7000f03c 0x1b4 0x7000f03c 0x1b4
0x7000f200 0x028 0x7000f200 0x028
0x7000f284 0x17c>; 0x7000f284 0x17c>;
interrupts = <0 77 0x04>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
}; };
iommu { iommu {
@ -457,7 +459,7 @@
compatible = "nvidia,tegra30-ahub"; compatible = "nvidia,tegra30-ahub";
reg = <0x70080000 0x200 reg = <0x70080000 0x200
0x70080200 0x100>; 0x70080200 0x100>;
interrupts = <0 103 0x04>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
nvidia,dma-request-selector = <&apbdma 1>; nvidia,dma-request-selector = <&apbdma 1>;
clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
@ -514,7 +516,7 @@
sdhci@78000000 { sdhci@78000000 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000000 0x200>; reg = <0x78000000 0x200>;
interrupts = <0 14 0x04>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 14>; clocks = <&tegra_car 14>;
status = "disabled"; status = "disabled";
}; };
@ -522,7 +524,7 @@
sdhci@78000200 { sdhci@78000200 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000200 0x200>; reg = <0x78000200 0x200>;
interrupts = <0 15 0x04>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 9>; clocks = <&tegra_car 9>;
status = "disabled"; status = "disabled";
}; };
@ -530,7 +532,7 @@
sdhci@78000400 { sdhci@78000400 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000400 0x200>; reg = <0x78000400 0x200>;
interrupts = <0 19 0x04>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 69>; clocks = <&tegra_car 69>;
status = "disabled"; status = "disabled";
}; };
@ -538,7 +540,7 @@
sdhci@78000600 { sdhci@78000600 {
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
reg = <0x78000600 0x200>; reg = <0x78000600 0x200>;
interrupts = <0 31 0x04>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car 15>; clocks = <&tegra_car 15>;
status = "disabled"; status = "disabled";
}; };
@ -574,9 +576,9 @@
pmu { pmu {
compatible = "arm,cortex-a9-pmu"; compatible = "arm,cortex-a9-pmu";
interrupts = <0 144 0x04 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
0 145 0x04 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
0 146 0x04 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
0 147 0x04>; <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
}; };
}; };