drm/amd/powerplay: add parts of system clock gating support for Fiji. (v2)
Removed fiji_mgcg_cgcg_init that is affected and redundant for new implementation. v2: re-add mgcg_cgcg init Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
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@ -1543,9 +1543,95 @@ static int vi_common_soft_reset(void *handle)
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return 0;
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}
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static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t temp, data;
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temp = data = RREG32_PCIE(ixPCIE_CNTL2);
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if (enable)
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data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
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else
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data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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if (temp != data)
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WREG32_PCIE(ixPCIE_CNTL2, data);
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}
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static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t temp, data;
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temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
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if (enable)
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data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
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else
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data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
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if (temp != data)
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WREG32(mmHDP_HOST_PATH_CNTL, data);
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}
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static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t temp, data;
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temp = data = RREG32(mmHDP_MEM_POWER_LS);
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if (enable)
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data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
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else
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data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
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if (temp != data)
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WREG32(mmHDP_MEM_POWER_LS, data);
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}
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static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t temp, data;
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temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
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if (enable)
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data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
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CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
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else
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data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
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CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
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if (temp != data)
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WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
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}
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static int vi_common_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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switch (adev->asic_type) {
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case CHIP_FIJI:
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fiji_update_bif_medium_grain_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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fiji_update_hdp_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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fiji_update_hdp_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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fiji_update_rom_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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break;
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default:
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break;
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}
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return 0;
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}
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