Bitmain SoC changes for v5.2:
- Added GPIO support for BM1880 SoC based on Designware APB GPIO controller - Added GPIO line names for Sophon Edge board based on 96Boards CE specification for accessing GPIOs using line names from userspace tools like MRAA. - Added pinctrl node for BM1880 SoC as a child node of sctrl syscon node. - Added pinctrl support to UARTs exposed on the Sophon Edge board. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEZ6VDKoFIy9ikWCeXVZ8R5v6RzvUFAlzGixQACgkQVZ8R5v6R zvXzAwgAn+KrTa0tM+HdDFwW8S9jzPll9zOj5YcTSvopecsUu1d+qGy4knd3Ufev HzeuD8gfUfxqaZ5nX9yETQ7XH6zwz4kTvGLh3jHhkdZ+SH7AYEdro9d8fEx71YD1 dEoUXSws5lWrvUusPzSsjWYCMbCOooBgXV2BjgK+jmVhE6HIDNSzIkQLrWRAgcxz V5VyLw2p+4vwY8cPBs7K6N8u453y1a5zcK3644a6dw58vqTRtg5++Acp0xrXg66b adFzIsUAto9W8mvwFYHwYty2NvdRWsSSnlZqfo8fopeUYUnzFKnlEHptisMcYuux ITN7ZkQFjVFKGXUZTV1CK4rIAby2kA== =7o9e -----END PGP SIGNATURE----- Merge tag 'bitmain-soc-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain into arm/dt Bitmain SoC changes for v5.2: - Added GPIO support for BM1880 SoC based on Designware APB GPIO controller - Added GPIO line names for Sophon Edge board based on 96Boards CE specification for accessing GPIOs using line names from userspace tools like MRAA. - Added pinctrl node for BM1880 SoC as a child node of sctrl syscon node. - Added pinctrl support to UARTs exposed on the Sophon Edge board. * tag 'bitmain-soc-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain: arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge arm64: dts: bitmain: Add pinctrl support for BM1880 SoC arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board arm64: dts: bitmain: Add GPIO support for BM1880 SoC Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
6cbc4d88ad
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@ -8,6 +8,28 @@
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#include "bm1880.dtsi"
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/*
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* GPIO name legend: proper name = the GPIO line is used as GPIO
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* NC = not connected (pin out but not routed from the chip to
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* anything the board)
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* "[PER]" = pin is muxed for [peripheral] (not GPIO)
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* LSEC = Low Speed External Connector
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* HSEC = High Speed External Connector
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*
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* Line names are taken from the schematic "sophon-edge-schematics"
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* version, 1.0210.
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*
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* For the lines routed to the external connectors the
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* lines are named after the 96Boards CE Specification 1.0,
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* Appendix "Expansion Connector Signal Description".
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*
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* When the 96Board naming of a line and the schematic name of
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* the same line are in conflict, the 96Board specification
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* takes precedence. This is only for the informational
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* lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
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* are the only ones actually used for GPIO.
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*/
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/ {
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compatible = "bitmain,sophon-edge", "bitmain,bm1880";
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model = "Sophon Edge";
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@ -32,19 +54,140 @@
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clock-frequency = <500000000>;
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#clock-cells = <0>;
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};
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soc {
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gpio0: gpio@50027000 {
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porta: gpio-controller@0 {
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gpio-line-names =
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"GPIO-A", /* GPIO0, LSEC pin 23 */
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"GPIO-C", /* GPIO1, LSEC pin 25 */
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"[GPIO2_PHY0_RST]", /* GPIO2 */
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"GPIO-E", /* GPIO3, LSEC pin 27 */
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"[USB_DET]", /* GPIO4 */
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"[EN_P5V]", /* GPIO5 */
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"[VDDIO_MS1_SEL]", /* GPIO6 */
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"GPIO-G", /* GPIO7, LSEC pin 29 */
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"[BM_TUSB_RST_L]", /* GPIO8 */
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"[EN_P5V_USBHUB]", /* GPIO9 */
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"NC",
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"LED_WIFI", /* GPIO11 */
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"LED_BT", /* GPIO12 */
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"[BM_BLM8221_EN_L]", /* GPIO13 */
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"NC", /* GPIO14 */
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"NC", /* GPIO15 */
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"NC", /* GPIO16 */
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"NC", /* GPIO17 */
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"NC", /* GPIO18 */
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"NC", /* GPIO19 */
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"NC", /* GPIO20 */
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"NC", /* GPIO21 */
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"NC", /* GPIO22 */
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"NC", /* GPIO23 */
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"NC", /* GPIO24 */
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"NC", /* GPIO25 */
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"NC", /* GPIO26 */
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"NC", /* GPIO27 */
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"NC", /* GPIO28 */
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"NC", /* GPIO29 */
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"NC", /* GPIO30 */
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"NC"; /* GPIO31 */
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};
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};
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gpio1: gpio@50027400 {
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portb: gpio-controller@0 {
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gpio-line-names =
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"NC", /* GPIO32 */
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"NC", /* GPIO33 */
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"[I2C0_SDA]", /* GPIO34, LSEC pin 17 */
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"[I2C0_SCL]", /* GPIO35, LSEC pin 15 */
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"[JTAG0_TDO]", /* GPIO36 */
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"[JTAG0_TCK]", /* GPIO37 */
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"[JTAG0_TDI]", /* GPIO38 */
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"[JTAG0_TMS]", /* GPIO39 */
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"[JTAG0_TRST_X]", /* GPIO40 */
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"[JTAG1_TDO]", /* GPIO41 */
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"[JTAG1_TCK]", /* GPIO42 */
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"[JTAG1_TDI]", /* GPIO43 */
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"[CPU_TX]", /* GPIO44 */
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"[CPU_RX]", /* GPIO45 */
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"[UART1_TXD]", /* GPIO46 */
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"[UART1_RXD]", /* GPIO47 */
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"[UART0_TXD]", /* GPIO48 */
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"[UART0_RXD]", /* GPIO49 */
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"GPIO-I", /* GPIO50, LSEC pin 31 */
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"GPIO-K", /* GPIO51, LSEC pin 33 */
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"USER_LED2", /* GPIO52 */
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"USER_LED1", /* GPIO53 */
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"[UART0_RTS]", /* GPIO54 */
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"[UART0_CTS]", /* GPIO55 */
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"USER_LED4", /* GPIO56, JTAG1_TRST_X */
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"USER_LED3", /* GPIO57, JTAG1_TMS */
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"[I2S0_SCLK]", /* GPIO58 */
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"[I2S0_FS]", /* GPIO59 */
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"[I2S0_SDI]", /* GPIO60 */
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"[I2S0_SDO]", /* GPIO61 */
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"GPIO-B", /* GPIO62, LSEC pin 24 */
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"GPIO-F"; /* GPIO63, I2S1_SCLK, LSEC pin 28 */
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};
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};
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gpio2: gpio@50027800 {
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portc: gpio-controller@0 {
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gpio-line-names =
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"GPIO-D", /* GPIO64, I2S1_FS, LSEC pin 26 */
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"GPIO-J", /* GPIO65, I2S1_SDI, LSEC pin 32 */
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"GPIO-H", /* GPIO66, I2S1_SDO, LSEC pin 30 */
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"GPIO-L", /* GPIO67, LSEC pin 34 */
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"[SPI0_CS]", /* GPIO68, SPI1_CS, LSEC pin 12 */
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"[SPI0_DIN]", /* GPIO69, SPI1_SDI, LSEC pin 10 */
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"[SPI0_DOUT]", /* GPIO70, SPI1_SDO, LSEC pin 14 */
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"[SPI0_SCLK]"; /* GPIO71, SPI1_SCK, LSEC pin 8 */
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};
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};
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};
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};
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&pinctrl {
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pinctrl_uart0_default: pinctrl-uart0-default {
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pinmux {
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groups = "uart0_grp";
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function = "uart0";
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};
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};
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pinctrl_uart1_default: pinctrl-uart1-default {
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pinmux {
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groups = "uart1_grp";
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function = "uart1";
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};
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};
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pinctrl_uart2_default: pinctrl-uart2-default {
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pinmux {
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groups = "uart2_grp";
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function = "uart2";
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};
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};
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};
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&uart0 {
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status = "okay";
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clocks = <&uart_clk>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0_default>;
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};
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&uart1 {
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status = "okay";
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clocks = <&uart_clk>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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&uart2 {
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status = "okay";
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clocks = <&uart_clk>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_default>;
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};
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@ -80,6 +80,74 @@
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#interrupt-cells = <3>;
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};
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sctrl: system-controller@50010000 {
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compatible = "bitmain,bm1880-sctrl", "syscon",
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"simple-mfd";
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reg = <0x0 0x50010000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x50010000 0x1000>;
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pinctrl: pinctrl@50 {
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compatible = "bitmain,bm1880-pinctrl";
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reg = <0x50 0x4B0>;
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};
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};
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gpio0: gpio@50027000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x50027000 0x0 0x400>;
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio1: gpio@50027400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x50027400 0x0 0x400>;
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio2: gpio@50027800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x50027800 0x0 0x400>;
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portc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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uart0: serial@58018000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x58018000 0x0 0x2000>;
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