ARM: proc-arm94*.S: fix setup function
Both ARM946 and ARM940 setup functions were corrupting r1 and r2, which is not permissible - these are used to carry the machine ID and boot data into the kernel, and must be preserved. The code responsible for this was the same in both files: they were using the registers to generate a protection region register value. Fix this by turning this process into a macro, and using that macro in both these files with an alternative register allocation. r0, r3 and r7 can be used for temporary values here. Reported-by: Alex Dumitrache <broscutamaker@gmail.com> Tested-by: Georg Hofstetter <g3gg0.de@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -297,26 +297,16 @@ __arm940_setup:
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mcr p15, 0, r0, c6, c0, 1
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ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
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ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the area register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
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mcr p15, 0, r0, c6, c1, 1
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ldr r7, =CONFIG_DRAM_SIZE >> 12 @ size of RAM (must be >= 4KB)
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pr_val r3, r0, r7, #1
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mcr p15, 0, r3, c6, c1, 0 @ set area 1, RAM
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mcr p15, 0, r3, c6, c1, 1
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ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
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ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the area register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
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mcr p15, 0, r0, c6, c2, 1
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ldr r7, =CONFIG_FLASH_SIZE @ size of FLASH (must be >= 4KB)
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pr_val r3, r0, r6, #1
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mcr p15, 0, r3, c6, c2, 0 @ set area 2, ROM/FLASH
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mcr p15, 0, r3, c6, c2, 1
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mov r0, #0x06
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mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
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@ -343,24 +343,14 @@ __arm946_setup:
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mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
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ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
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ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the region register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM
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ldr r7, =CONFIG_DRAM_SIZE @ size of RAM (must be >= 4KB)
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pr_val r3, r0, r7, #1
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mcr p15, 0, r3, c6, c1, 0
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ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
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ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the region register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH
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ldr r7, =CONFIG_FLASH_SIZE @ size of FLASH (must be >= 4KB)
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pr_val r3, r0, r7, #1
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mcr p15, 0, r3, c6, c2, 0
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mov r0, #0x06
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mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
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@ -331,3 +331,27 @@ ENTRY(\name\()_tlb_fns)
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.globl \x
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.equ \x, \y
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.endm
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/*
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* Macro to calculate the log2 size for the protection region
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* registers. This calculates rd = log2(size) - 1. tmp must
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* not be the same register as rd.
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*/
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.macro pr_sz, rd, size, tmp
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mov \tmp, \size, lsr #12
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mov \rd, #11
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1: movs \tmp, \tmp, lsr #1
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addne \rd, \rd, #1
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bne 1b
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.endm
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/*
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* Macro to generate a protection region register value
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* given a pre-masked address, size, and enable bit.
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* Corrupts size.
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*/
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.macro pr_val, dest, addr, size, enable
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pr_sz \dest, \size, \size @ calculate log2(size) - 1
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orr \dest, \addr, \dest, lsl #1 @ mask in the region size
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orr \dest, \dest, \enable
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.endm
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