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bnx2x: Revise prints 

This patch revises many bnx2x prints - mainly fixing print typos and
adding some new debug prints (mostly for parity issues).

Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: Ariel Elior <ariele@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yuval Mintz 2013-06-02 00:06:20 +00:00 committed by David S. Miller
parent 3cdeec22e4
commit 6bf07b8e36
9 changed files with 225 additions and 85 deletions
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1
drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
View File

@ -1900,7 +1900,6 @@ u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
u8 src_type, u8 dst_type); u8 src_type, u8 dst_type);
int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae); int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae);
void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl);
/* FLR related routines */ /* FLR related routines */
u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);

8
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
View File

@ -2162,10 +2162,10 @@ static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
bp->fw_stats_data_mapping = bp->fw_stats_mapping + bp->fw_stats_data_mapping = bp->fw_stats_mapping +
bp->fw_stats_req_sz; bp->fw_stats_req_sz;
DP(BNX2X_MSG_SP, "statistics request base address set to %x %x", DP(BNX2X_MSG_SP, "statistics request base address set to %x %x\n",
U64_HI(bp->fw_stats_req_mapping), U64_HI(bp->fw_stats_req_mapping),
U64_LO(bp->fw_stats_req_mapping)); U64_LO(bp->fw_stats_req_mapping));
DP(BNX2X_MSG_SP, "statistics data base address set to %x %x", DP(BNX2X_MSG_SP, "statistics data base address set to %x %x\n",
U64_HI(bp->fw_stats_data_mapping), U64_HI(bp->fw_stats_data_mapping),
U64_LO(bp->fw_stats_data_mapping)); U64_LO(bp->fw_stats_data_mapping));
return 0; return 0;
@ -2240,7 +2240,7 @@ int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code)
/* abort nic load if version mismatch */ /* abort nic load if version mismatch */
if (my_fw != loaded_fw) { if (my_fw != loaded_fw) {
BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. aborting\n", BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. Aborting\n",
loaded_fw, my_fw); loaded_fw, my_fw);
return -EBUSY; return -EBUSY;
} }
@ -3977,7 +3977,7 @@ int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
/* requested to support too many traffic classes */ /* requested to support too many traffic classes */
if (num_tc > bp->max_cos) { if (num_tc > bp->max_cos) {
BNX2X_ERR("support for too many traffic classes requested: %d. max supported is %d\n", BNX2X_ERR("support for too many traffic classes requested: %d. Max supported is %d\n",
num_tc, bp->max_cos); num_tc, bp->max_cos);
return -EINVAL; return -EINVAL;
} }

2
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
View File

@ -55,6 +55,8 @@ do { \
GFP_KERNEL | __GFP_ZERO); \ GFP_KERNEL | __GFP_ZERO); \
if (x == NULL) \ if (x == NULL) \
goto alloc_mem_err; \ goto alloc_mem_err; \
DP(NETIF_MSG_HW, "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \
(unsigned long long)(*y), x); \
} while (0) } while (0)
#define BNX2X_ALLOC(x, size) \ #define BNX2X_ALLOC(x, size) \

4
drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
View File

@ -2381,7 +2381,7 @@ static u8 bnx2x_dcbnl_get_featcfg(struct net_device *netdev, int featid,
*flags |= DCB_FEATCFG_ERROR; *flags |= DCB_FEATCFG_ERROR;
break; break;
default: default:
BNX2X_ERR("Non valid featrue-ID\n"); BNX2X_ERR("Non valid feature-ID\n");
rval = 1; rval = 1;
break; break;
} }
@ -2422,7 +2422,7 @@ static u8 bnx2x_dcbnl_set_featcfg(struct net_device *netdev, int featid,
flags & DCB_FEATCFG_WILLING ? 1 : 0; flags & DCB_FEATCFG_WILLING ? 1 : 0;
break; break;
default: default:
BNX2X_ERR("Non valid featrue-ID\n"); BNX2X_ERR("Non valid feature-ID\n");
rval = 1; rval = 1;
break; break;
} }

385
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
View File

@ -371,9 +371,11 @@ static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
#define DMAE_DP_DST_NONE "dst_addr [none]" #define DMAE_DP_DST_NONE "dst_addr [none]"
void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl) static void bnx2x_dp_dmae(struct bnx2x *bp,
struct dmae_command *dmae, int msglvl)
{ {
u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
int i;
switch (dmae->opcode & DMAE_COMMAND_DST) { switch (dmae->opcode & DMAE_COMMAND_DST) {
case DMAE_CMD_DST_PCI: case DMAE_CMD_DST_PCI:
@ -429,6 +431,10 @@ void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
dmae->comp_val); dmae->comp_val);
break; break;
} }
for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
i, *(((u32 *)dmae) + i));
} }
/* copy command into DMAE command memory and set DMAE command go */ /* copy command into DMAE command memory and set DMAE command go */
@ -503,8 +509,9 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
int rc = 0; int rc = 0;
/* bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
* Lock the dmae channel. Disable BHs to prevent a dead-lock
/* Lock the dmae channel. Disable BHs to prevent a dead-lock
* as long as this code is called both from syscall context and * as long as this code is called both from syscall context and
* from ndo_set_rx_mode() flow that may be called from BH. * from ndo_set_rx_mode() flow that may be called from BH.
*/ */
@ -543,6 +550,7 @@ unlock:
void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
u32 len32) u32 len32)
{ {
int rc;
struct dmae_command dmae; struct dmae_command dmae;
if (!bp->dmae_ready) { if (!bp->dmae_ready) {
@ -566,11 +574,16 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
dmae.len = len32; dmae.len = len32;
/* issue the command and wait for completion */ /* issue the command and wait for completion */
bnx2x_issue_dmae_with_comp(bp, &dmae); rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
if (rc) {
BNX2X_ERR("DMAE returned failure %d\n", rc);
bnx2x_panic();
}
} }
void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
{ {
int rc;
struct dmae_command dmae; struct dmae_command dmae;
if (!bp->dmae_ready) { if (!bp->dmae_ready) {
@ -598,7 +611,11 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
dmae.len = len32; dmae.len = len32;
/* issue the command and wait for completion */ /* issue the command and wait for completion */
bnx2x_issue_dmae_with_comp(bp, &dmae); rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
if (rc) {
BNX2X_ERR("DMAE returned failure %d\n", rc);
bnx2x_panic();
};
} }
static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
@ -834,7 +851,7 @@ static void bnx2x_hc_int_disable(struct bnx2x *bp)
REG_WR(bp, addr, val); REG_WR(bp, addr, val);
if (REG_RD(bp, addr) != val) if (REG_RD(bp, addr) != val)
BNX2X_ERR("BUG! proper val not read from IGU!\n"); BNX2X_ERR("BUG! Proper val not read from IGU!\n");
} }
static void bnx2x_igu_int_disable(struct bnx2x *bp) static void bnx2x_igu_int_disable(struct bnx2x *bp)
@ -852,7 +869,7 @@ static void bnx2x_igu_int_disable(struct bnx2x *bp)
REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
BNX2X_ERR("BUG! proper val not read from IGU!\n"); BNX2X_ERR("BUG! Proper val not read from IGU!\n");
} }
static void bnx2x_int_disable(struct bnx2x *bp) static void bnx2x_int_disable(struct bnx2x *bp)
@ -1021,6 +1038,7 @@ void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
#ifdef BNX2X_STOP_ON_ERROR #ifdef BNX2X_STOP_ON_ERROR
/* event queue */ /* event queue */
BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
for (i = 0; i < NUM_EQ_DESC; i++) { for (i = 0; i < NUM_EQ_DESC; i++) {
u32 *data = (u32 *)&bp->eq_ring[i].message.data; u32 *data = (u32 *)&bp->eq_ring[i].message.data;
@ -1379,7 +1397,7 @@ static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
/* Wait DMAE PF usage counter to zero */ /* Wait DMAE PF usage counter to zero */
if (bnx2x_flr_clnup_poll_hw_counter(bp, if (bnx2x_flr_clnup_poll_hw_counter(bp,
dmae_reg_go_c[INIT_DMAE_C(bp)], dmae_reg_go_c[INIT_DMAE_C(bp)],
"DMAE dommand register timed out", "DMAE command register timed out",
poll_cnt)) poll_cnt))
return 1; return 1;
@ -1759,7 +1777,7 @@ void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
break; break;
case (RAMROD_CMD_ID_ETH_TERMINATE): case (RAMROD_CMD_ID_ETH_TERMINATE):
DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
drv_cmd = BNX2X_Q_CMD_TERMINATE; drv_cmd = BNX2X_Q_CMD_TERMINATE;
break; break;
@ -1971,7 +1989,7 @@ int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
/* Validating that the resource is currently taken */ /* Validating that the resource is currently taken */
lock_status = REG_RD(bp, hw_lock_control_reg); lock_status = REG_RD(bp, hw_lock_control_reg);
if (!(lock_status & resource_bit)) { if (!(lock_status & resource_bit)) {
BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
lock_status, resource_bit); lock_status, resource_bit);
return -EFAULT; return -EFAULT;
} }
@ -4237,13 +4255,18 @@ static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
return val != 0; return val != 0;
} }
static void _print_parity(struct bnx2x *bp, u32 reg)
{
pr_cont(" [0x%08x] ", REG_RD(bp, reg));
}
static void _print_next_block(int idx, const char *blk) static void _print_next_block(int idx, const char *blk)
{ {
pr_cont("%s%s", idx ? ", " : "", blk); pr_cont("%s%s", idx ? ", " : "", blk);
} }
static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
bool print) int par_num, bool print)
{ {
int i = 0; int i = 0;
u32 cur_bit = 0; u32 cur_bit = 0;
@ -4252,33 +4275,54 @@ static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
if (sig & cur_bit) { if (sig & cur_bit) {
switch (cur_bit) { switch (cur_bit) {
case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "BRB"); _print_next_block(par_num++, "BRB");
_print_parity(bp,
BRB1_REG_BRB1_PRTY_STS);
}
break; break;
case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "PARSER"); _print_next_block(par_num++, "PARSER");
_print_parity(bp, PRS_REG_PRS_PRTY_STS);
}
break; break;
case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "TSDM"); _print_next_block(par_num++, "TSDM");
_print_parity(bp,
TSDM_REG_TSDM_PRTY_STS);
}
break; break;
case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, _print_next_block(par_num++,
"SEARCHER"); "SEARCHER");
_print_parity(bp, SRC_REG_SRC_PRTY_STS);
}
break; break;
case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "TCM"); _print_next_block(par_num++, "TCM");
_print_parity(bp,
TCM_REG_TCM_PRTY_STS);
}
break; break;
case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "TSEMI"); _print_next_block(par_num++, "TSEMI");
_print_parity(bp,
TSEM_REG_TSEM_PRTY_STS_0);
_print_parity(bp,
TSEM_REG_TSEM_PRTY_STS_1);
}
break; break;
case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "XPB"); _print_next_block(par_num++, "XPB");
_print_parity(bp, GRCBASE_XPB +
PB_REG_PB_PRTY_STS);
}
break; break;
} }
@ -4290,93 +4334,8 @@ static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
return par_num; return par_num;
} }
static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
bool *global, bool print) int par_num, bool *global,
{
int i = 0;
u32 cur_bit = 0;
for (i = 0; sig; i++) {
cur_bit = ((u32)0x1 << i);
if (sig & cur_bit) {
switch (cur_bit) {
case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "PBF");
break;
case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "QM");
break;
case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "TM");
break;
case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "XSDM");
break;
case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "XCM");
break;
case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "XSEMI");
break;
case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
if (print)
_print_next_block(par_num++,
"DOORBELLQ");
break;
case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "NIG");
break;
case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
if (print)
_print_next_block(par_num++,
"VAUX PCI CORE");
*global = true;
break;
case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "DEBUG");
break;
case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "USDM");
break;
case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "UCM");
break;
case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "USEMI");
break;
case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "UPB");
break;
case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "CSDM");
break;
case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
if (print)
_print_next_block(par_num++, "CCM");
break;
}
/* Clear the bit */
sig &= ~cur_bit;
}
}
return par_num;
}
static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
bool print) bool print)
{ {
int i = 0; int i = 0;
@ -4385,13 +4344,159 @@ static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
cur_bit = ((u32)0x1 << i); cur_bit = ((u32)0x1 << i);
if (sig & cur_bit) { if (sig & cur_bit) {
switch (cur_bit) { switch (cur_bit) {
case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "PBF");
_print_parity(bp, PBF_REG_PBF_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "QM");
_print_parity(bp, QM_REG_QM_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "TM");
_print_parity(bp, TM_REG_TM_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "XSDM");
_print_parity(bp,
XSDM_REG_XSDM_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "XCM");
_print_parity(bp, XCM_REG_XCM_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "XSEMI");
_print_parity(bp,
XSEM_REG_XSEM_PRTY_STS_0);
_print_parity(bp,
XSEM_REG_XSEM_PRTY_STS_1);
}
break;
case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
if (print) {
_print_next_block(par_num++,
"DOORBELLQ");
_print_parity(bp,
DORQ_REG_DORQ_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "NIG");
if (CHIP_IS_E1x(bp)) {
_print_parity(bp,
NIG_REG_NIG_PRTY_STS);
} else {
_print_parity(bp,
NIG_REG_NIG_PRTY_STS_0);
_print_parity(bp,
NIG_REG_NIG_PRTY_STS_1);
}
}
break;
case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
if (print) if (print)
_print_next_block(par_num++,
"VAUX PCI CORE");
*global = true;
break;
case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "DEBUG");
_print_parity(bp, DBG_REG_DBG_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "USDM");
_print_parity(bp,
USDM_REG_USDM_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "UCM");
_print_parity(bp, UCM_REG_UCM_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "USEMI");
_print_parity(bp,
USEM_REG_USEM_PRTY_STS_0);
_print_parity(bp,
USEM_REG_USEM_PRTY_STS_1);
}
break;
case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "UPB");
_print_parity(bp, GRCBASE_UPB +
PB_REG_PB_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "CSDM");
_print_parity(bp,
CSDM_REG_CSDM_PRTY_STS);
}
break;
case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "CCM");
_print_parity(bp, CCM_REG_CCM_PRTY_STS);
}
break;
}
/* Clear the bit */
sig &= ~cur_bit;
}
}
return par_num;
}
static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
int par_num, bool print)
{
int i = 0;
u32 cur_bit = 0;
for (i = 0; sig; i++) {
cur_bit = ((u32)0x1 << i);
if (sig & cur_bit) {
switch (cur_bit) {
case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
if (print) {
_print_next_block(par_num++, "CSEMI"); _print_next_block(par_num++, "CSEMI");
_print_parity(bp,
CSEM_REG_CSEM_PRTY_STS_0);
_print_parity(bp,
CSEM_REG_CSEM_PRTY_STS_1);
}
break; break;
case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "PXP"); _print_next_block(par_num++, "PXP");
_print_parity(bp, PXP_REG_PXP_PRTY_STS);
_print_parity(bp,
PXP2_REG_PXP2_PRTY_STS_0);
_print_parity(bp,
PXP2_REG_PXP2_PRTY_STS_1);
}
break; break;
case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
if (print) if (print)
@ -4399,24 +4504,42 @@ static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
"PXPPCICLOCKCLIENT"); "PXPPCICLOCKCLIENT");
break; break;
case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "CFC"); _print_next_block(par_num++, "CFC");
_print_parity(bp,
CFC_REG_CFC_PRTY_STS);
}
break; break;
case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "CDU"); _print_next_block(par_num++, "CDU");
_print_parity(bp, CDU_REG_CDU_PRTY_STS);
}
break; break;
case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "DMAE"); _print_next_block(par_num++, "DMAE");
_print_parity(bp,
DMAE_REG_DMAE_PRTY_STS);
}
break; break;
case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "IGU"); _print_next_block(par_num++, "IGU");
if (CHIP_IS_E1x(bp))
_print_parity(bp,
HC_REG_HC_PRTY_STS);
else
_print_parity(bp,
IGU_REG_IGU_PRTY_STS);
}
break; break;
case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "MISC"); _print_next_block(par_num++, "MISC");
_print_parity(bp,
MISC_REG_MISC_PRTY_STS);
}
break; break;
} }
@ -4470,8 +4593,8 @@ static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
return par_num; return par_num;
} }
static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
bool print) int par_num, bool print)
{ {
int i = 0; int i = 0;
u32 cur_bit = 0; u32 cur_bit = 0;
@ -4480,12 +4603,18 @@ static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
if (sig & cur_bit) { if (sig & cur_bit) {
switch (cur_bit) { switch (cur_bit) {
case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "PGLUE_B"); _print_next_block(par_num++, "PGLUE_B");
_print_parity(bp,
PGLUE_B_REG_PGLUE_B_PRTY_STS);
}
break; break;
case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
if (print) if (print) {
_print_next_block(par_num++, "ATC"); _print_next_block(par_num++, "ATC");
_print_parity(bp,
ATC_REG_ATC_PRTY_STS);
}
break; break;
} }
@ -4516,15 +4645,15 @@ static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
if (print) if (print)
netdev_err(bp->dev, netdev_err(bp->dev,
"Parity errors detected in blocks: "); "Parity errors detected in blocks: ");
par_num = bnx2x_check_blocks_with_parity0( par_num = bnx2x_check_blocks_with_parity0(bp,
sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
par_num = bnx2x_check_blocks_with_parity1( par_num = bnx2x_check_blocks_with_parity1(bp,
sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
par_num = bnx2x_check_blocks_with_parity2( par_num = bnx2x_check_blocks_with_parity2(bp,
sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
par_num = bnx2x_check_blocks_with_parity3( par_num = bnx2x_check_blocks_with_parity3(
sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
par_num = bnx2x_check_blocks_with_parity4( par_num = bnx2x_check_blocks_with_parity4(bp,
sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
if (print) if (print)
@ -7437,7 +7566,7 @@ static int bnx2x_init_hw_func(struct bnx2x *bp)
} else { } else {
/* Set NIC mode */ /* Set NIC mode */
REG_WR(bp, PRS_REG_NIC_MODE, 1); REG_WR(bp, PRS_REG_NIC_MODE, 1);
DP(NETIF_MSG_IFUP, "NIC MODE configrued\n"); DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
} }
if (!CHIP_IS_E1x(bp)) { if (!CHIP_IS_E1x(bp)) {
@ -8609,7 +8738,7 @@ static int bnx2x_func_wait_started(struct bnx2x *bp)
struct bnx2x_func_state_params func_params = {NULL}; struct bnx2x_func_state_params func_params = {NULL};
DP(NETIF_MSG_IFDOWN, DP(NETIF_MSG_IFDOWN,
"Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
func_params.f_obj = &bp->func_obj; func_params.f_obj = &bp->func_obj;
__set_bit(RAMROD_DRV_CLR_ONLY, __set_bit(RAMROD_DRV_CLR_ONLY,
@ -9426,14 +9555,12 @@ static void bnx2x_sp_rtnl_task(struct work_struct *work)
return; return;
} }
/* if stop on error is defined no recovery flows should be executed */ if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
#ifdef BNX2X_STOP_ON_ERROR #ifdef BNX2X_STOP_ON_ERROR
BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
"you will need to reboot when done\n"); "you will need to reboot when done\n");
goto sp_rtnl_not_reset; goto sp_rtnl_not_reset;
#endif #endif
if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
/* /*
* Clear all pending SP commands as we are going to reset the * Clear all pending SP commands as we are going to reset the
* function anyway. * function anyway.
@ -9448,6 +9575,12 @@ static void bnx2x_sp_rtnl_task(struct work_struct *work)
} }
if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
#ifdef BNX2X_STOP_ON_ERROR
BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
"you will need to reboot when done\n");
goto sp_rtnl_not_reset;
#endif
/* /*
* Clear all pending SP commands as we are going to reset the * Clear all pending SP commands as we are going to reset the
* function anyway. * function anyway.

6
drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
View File

@ -35,6 +35,8 @@
#define ATC_REG_ATC_INT_STS_CLR 0x1101c0 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
/* [RW 5] Parity mask register #0 read/write */ /* [RW 5] Parity mask register #0 read/write */
#define ATC_REG_ATC_PRTY_MASK 0x1101d8 #define ATC_REG_ATC_PRTY_MASK 0x1101d8
/* [R 5] Parity register #0 read */
#define ATC_REG_ATC_PRTY_STS 0x1101cc
/* [RC 5] Parity register #0 read clear */ /* [RC 5] Parity register #0 read clear */
#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0 #define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
/* [RW 19] Interrupt mask register #0 read/write */ /* [RW 19] Interrupt mask register #0 read/write */
@ -2750,6 +2752,8 @@
#define PBF_REG_PBF_INT_STS 0x1401c8 #define PBF_REG_PBF_INT_STS 0x1401c8
/* [RW 20] Parity mask register #0 read/write */ /* [RW 20] Parity mask register #0 read/write */
#define PBF_REG_PBF_PRTY_MASK 0x1401e4 #define PBF_REG_PBF_PRTY_MASK 0x1401e4
/* [R 28] Parity register #0 read */
#define PBF_REG_PBF_PRTY_STS 0x1401d8
/* [RC 20] Parity register #0 read clear */ /* [RC 20] Parity register #0 read clear */
#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
/* [RW 16] The Ethernet type value for L2 tag 0 */ /* [RW 16] The Ethernet type value for L2 tag 0 */
@ -4517,6 +4521,8 @@
#define TM_REG_TM_INT_STS 0x1640f0 #define TM_REG_TM_INT_STS 0x1640f0
/* [RW 7] Parity mask register #0 read/write */ /* [RW 7] Parity mask register #0 read/write */
#define TM_REG_TM_PRTY_MASK 0x16410c #define TM_REG_TM_PRTY_MASK 0x16410c
/* [R 7] Parity register #0 read */
#define TM_REG_TM_PRTY_STS 0x164100
/* [RC 7] Parity register #0 read clear */ /* [RC 7] Parity register #0 read clear */
#define TM_REG_TM_PRTY_STS_CLR 0x164104 #define TM_REG_TM_PRTY_STS_CLR 0x164104
/* [RW 8] The event id for aggregated interrupt 0 */ /* [RW 8] The event id for aggregated interrupt 0 */

6
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
View File

@ -1620,7 +1620,7 @@ next_vf_to_clean:
i++) i++)
; ;
DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. num of vfs: %d\n", i, DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n", i,
BNX2X_NR_VIRTFN(bp)); BNX2X_NR_VIRTFN(bp));
if (i < BNX2X_NR_VIRTFN(bp)) { if (i < BNX2X_NR_VIRTFN(bp)) {
@ -3031,7 +3031,7 @@ int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param)
/* HW channel is only operational when PF is up */ /* HW channel is only operational when PF is up */
if (bp->state != BNX2X_STATE_OPEN) { if (bp->state != BNX2X_STATE_OPEN) {
BNX2X_ERR("VF num configurtion via sysfs not supported while PF is down"); BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n");
return -EINVAL; return -EINVAL;
} }
@ -3391,7 +3391,7 @@ enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp)
if (bulletin.crc == bnx2x_crc_vf_bulletin(bp, if (bulletin.crc == bnx2x_crc_vf_bulletin(bp,
&bulletin)) &bulletin))
break; break;
BNX2X_ERR("bad crc on bulletin board. contained %x computed %x\n", BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n",
bulletin.crc, bulletin.crc,
bnx2x_crc_vf_bulletin(bp, &bulletin)); bnx2x_crc_vf_bulletin(bp, &bulletin));
} }

2
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h
View File

@ -496,7 +496,7 @@ enum {
else if ((next) == VFOP_VERIFY_PEND) \ else if ((next) == VFOP_VERIFY_PEND) \
BNX2X_ERR("expected pending\n"); \ BNX2X_ERR("expected pending\n"); \
else { \ else { \
DP(BNX2X_MSG_IOV, "no ramrod. scheduling\n"); \ DP(BNX2X_MSG_IOV, "no ramrod. Scheduling\n"); \
atomic_set(&vf->op_in_progress, 1); \ atomic_set(&vf->op_in_progress, 1); \
queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); \ queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); \
return; \ return; \

8
drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c
View File

@ -333,7 +333,7 @@ int bnx2x_vfpf_release(struct bnx2x *bp)
DP(BNX2X_MSG_SP, "vf released\n"); DP(BNX2X_MSG_SP, "vf released\n");
} else { } else {
/* PF reports error */ /* PF reports error */
BNX2X_ERR("PF failed our release request - are we out of sync? response status: %d\n", BNX2X_ERR("PF failed our release request - are we out of sync? Response status: %d\n",
resp->hdr.status); resp->hdr.status);
rc = -EAGAIN; rc = -EAGAIN;
goto out; goto out;
@ -844,7 +844,6 @@ static int bnx2x_copy32_vf_dmae(struct bnx2x *bp, u8 from_vf,
dmae.dst_addr_hi = vf_addr_hi; dmae.dst_addr_hi = vf_addr_hi;
} }
dmae.len = len32; dmae.len = len32;
bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_DMAE);
/* issue the command and wait for completion */ /* issue the command and wait for completion */
return bnx2x_issue_dmae_with_comp(bp, &dmae); return bnx2x_issue_dmae_with_comp(bp, &dmae);
@ -1588,8 +1587,9 @@ static void bnx2x_vf_mbx_request(struct bnx2x *bp, struct bnx2x_virtf *vf,
* support them. Or this may be because someone wrote a crappy * support them. Or this may be because someone wrote a crappy
* VF driver and is sending garbage over the channel. * VF driver and is sending garbage over the channel.
*/ */
BNX2X_ERR("unknown TLV. type %d length %d. first 20 bytes of mailbox buffer:\n", BNX2X_ERR("unknown TLV. type %d length %d vf->state was %d. first 20 bytes of mailbox buffer:\n",
mbx->first_tlv.tl.type, mbx->first_tlv.tl.length); mbx->first_tlv.tl.type, mbx->first_tlv.tl.length,
vf->state);
for (i = 0; i < 20; i++) for (i = 0; i < 20; i++)
DP_CONT(BNX2X_MSG_IOV, "%x ", DP_CONT(BNX2X_MSG_IOV, "%x ",
mbx->msg->req.tlv_buf_size.tlv_buffer[i]); mbx->msg->req.tlv_buf_size.tlv_buffer[i]);