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[ARM] xsc3: revert writethrough memory-type encoding change 

Commit 40df2d1d "[ARM] Update Xscale and Xscale3 PTE mappings" was
fingered by git-bisect for a boot failure on iop13xx.  The change made
L_PTE_MT_WRITETHROUGH mappings L2-uncacheable.  Russell points out that
this mapping is used for the vector page.  Given the regression, and the
fact this page is used often, restore the old behaviour.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams 2008-10-24 10:21:45 -07:00
parent e013e13bf6
commit 6bee00dbbc
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mm/proc-xsc3.S
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@ -349,7 +349,7 @@ ENTRY(cpu_xsc3_switch_mm)
cpu_xsc3_mt_table: cpu_xsc3_mt_table:
.long 0x00 @ L_PTE_MT_UNCACHED .long 0x00 @ L_PTE_MT_UNCACHED
.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
.long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
.long 0x00 @ unused .long 0x00 @ unused