Merge remote-tracking branches 'spi/topic/acpi', 'spi/topic/axi-engine', 'spi/topic/bcm2835' and 'spi/topic/bcm2835aux' into spi-next
This commit is contained in:
Mark Brown
commit
6beb9fecbd
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@ -0,0 +1,31 @@
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Analog Devices AXI SPI Engine controller Device Tree Bindings
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Required properties:
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- compatible : Must be "adi,axi-spi-engine-1.00.a""
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- reg : Physical base address and size of the register map.
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- interrupts : Property with a value describing the interrupt
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number.
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- clock-names : List of input clock names - "s_axi_aclk", "spi_clk"
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- clocks : Clock phandles and specifiers (See clock bindings for
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details on clock-names and clocks).
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- #address-cells : Must be <1>
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- #size-cells : Must be <0>
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Optional subnodes:
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Subnodes are use to represent the SPI slave devices connected to the SPI
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master. They follow the generic SPI bindings as outlined in spi-bus.txt.
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Example:
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spi@@44a00000 {
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compatible = "adi,axi-spi-engine-1.00.a";
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reg = <0x44a00000 0x1000>;
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interrupts = <0 56 4>;
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clocks = <&clkc 15 &clkc 15>;
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clock-names = "s_axi_aclk", "spi_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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/* SPI devices */
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};
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@ -75,11 +75,26 @@ config SPI_ATMEL
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This selects a driver for the Atmel SPI Controller, present on
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many AT32 (AVR32) and AT91 (ARM) chips.
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config SPI_AU1550
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tristate "Au1550/Au1200/Au1300 SPI Controller"
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depends on MIPS_ALCHEMY
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select SPI_BITBANG
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help
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If you say yes to this option, support will be included for the
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PSC SPI controller found on Au1550, Au1200 and Au1300 series.
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config SPI_AXI_SPI_ENGINE
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tristate "Analog Devices AXI SPI Engine controller"
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depends on HAS_IOMEM
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help
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This enables support for the Analog Devices AXI SPI Engine SPI controller.
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It is part of the SPI Engine framework that is used in some Analog Devices
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reference designs for FPGAs.
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config SPI_BCM2835
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tristate "BCM2835 SPI controller"
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depends on GPIOLIB
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depends on ARCH_BCM2835 || COMPILE_TEST
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depends on GPIOLIB
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help
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This selects a driver for the Broadcom BCM2835 SPI master.
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@ -90,8 +105,7 @@ config SPI_BCM2835
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config SPI_BCM2835AUX
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tristate "BCM2835 SPI auxiliary controller"
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depends on ARCH_BCM2835 || COMPILE_TEST
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depends on GPIOLIB
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depends on (ARCH_BCM2835 && GPIOLIB) || COMPILE_TEST
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help
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This selects a driver for the Broadcom BCM2835 SPI aux master.
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@ -118,14 +132,6 @@ config SPI_BFIN_SPORT
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help
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Enable support for a SPI bus via the Blackfin SPORT peripheral.
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config SPI_AU1550
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tristate "Au1550/Au1200/Au1300 SPI Controller"
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depends on MIPS_ALCHEMY
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select SPI_BITBANG
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help
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If you say yes to this option, support will be included for the
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PSC SPI controller found on Au1550, Au1200 and Au1300 series.
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config SPI_BCM53XX
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tristate "Broadcom BCM53xx SPI controller"
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depends on ARCH_BCM_5301X
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@ -197,6 +203,23 @@ config SPI_DAVINCI
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help
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SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules.
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config SPI_DESIGNWARE
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tristate "DesignWare SPI controller core support"
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help
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general driver for SPI controller core from DesignWare
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config SPI_DW_PCI
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tristate "PCI interface driver for DW SPI core"
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depends on SPI_DESIGNWARE && PCI
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config SPI_DW_MID_DMA
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bool "DMA support for DW SPI controller on Intel MID platform"
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depends on SPI_DW_PCI && DW_DMAC_PCI
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config SPI_DW_MMIO
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tristate "Memory-mapped io interface driver for DW SPI core"
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depends on SPI_DESIGNWARE
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config SPI_DLN2
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tristate "Diolan DLN-2 USB SPI adapter"
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depends on MFD_DLN2
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@ -346,6 +369,13 @@ config SPI_MT65XX
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say Y or M here.If you are not sure, say N.
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SPI drivers for Mediatek MT65XX and MT81XX series ARM SoCs.
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config SPI_NUC900
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tristate "Nuvoton NUC900 series SPI"
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depends on ARCH_W90X900
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select SPI_BITBANG
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help
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SPI driver for Nuvoton NUC900 series ARM SoCs
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config SPI_OC_TINY
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tristate "OpenCores tiny SPI"
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depends on GPIOLIB || COMPILE_TEST
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@ -647,34 +677,10 @@ config SPI_ZYNQMP_GQSPI
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help
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Enables Xilinx GQSPI controller driver for Zynq UltraScale+ MPSoC.
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config SPI_NUC900
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tristate "Nuvoton NUC900 series SPI"
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depends on ARCH_W90X900
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select SPI_BITBANG
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help
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SPI driver for Nuvoton NUC900 series ARM SoCs
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#
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# Add new SPI master controllers in alphabetical order above this line
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#
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config SPI_DESIGNWARE
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tristate "DesignWare SPI controller core support"
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help
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general driver for SPI controller core from DesignWare
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config SPI_DW_PCI
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tristate "PCI interface driver for DW SPI core"
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depends on SPI_DESIGNWARE && PCI
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config SPI_DW_MID_DMA
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bool "DMA support for DW SPI controller on Intel MID platform"
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depends on SPI_DW_PCI && DW_DMAC_PCI
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config SPI_DW_MMIO
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tristate "Memory-mapped io interface driver for DW SPI core"
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depends on SPI_DESIGNWARE
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#
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# There are lots of SPI device types, with sensors and memory
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# being probably the most widely used ones.
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@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
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obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
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obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
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obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
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obj-$(CONFIG_SPI_AXI_SPI_ENGINE) += spi-axi-spi-engine.o
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obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
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obj-$(CONFIG_SPI_BCM2835AUX) += spi-bcm2835aux.o
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obj-$(CONFIG_SPI_BCM53XX) += spi-bcm53xx.o
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@ -0,0 +1,591 @@
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/*
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* SPI-Engine SPI controller driver
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* Copyright 2015 Analog Devices Inc.
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* Author: Lars-Peter Clausen <lars@metafoo.de>
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*
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* Licensed under the GPL-2.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff)
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#define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff)
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#define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff)
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#define SPI_ENGINE_REG_VERSION 0x00
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#define SPI_ENGINE_REG_RESET 0x40
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#define SPI_ENGINE_REG_INT_ENABLE 0x80
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#define SPI_ENGINE_REG_INT_PENDING 0x84
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#define SPI_ENGINE_REG_INT_SOURCE 0x88
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#define SPI_ENGINE_REG_SYNC_ID 0xc0
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#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xd0
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#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xd4
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#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xd8
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#define SPI_ENGINE_REG_CMD_FIFO 0xe0
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#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xe4
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#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xe8
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#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec
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#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
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#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
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#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
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#define SPI_ENGINE_INT_SYNC BIT(3)
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#define SPI_ENGINE_CONFIG_CPHA BIT(0)
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#define SPI_ENGINE_CONFIG_CPOL BIT(1)
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#define SPI_ENGINE_CONFIG_3WIRE BIT(2)
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#define SPI_ENGINE_INST_TRANSFER 0x0
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#define SPI_ENGINE_INST_ASSERT 0x1
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#define SPI_ENGINE_INST_WRITE 0x2
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#define SPI_ENGINE_INST_MISC 0x3
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#define SPI_ENGINE_CMD_REG_CLK_DIV 0x0
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#define SPI_ENGINE_CMD_REG_CONFIG 0x1
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#define SPI_ENGINE_MISC_SYNC 0x0
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#define SPI_ENGINE_MISC_SLEEP 0x1
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#define SPI_ENGINE_TRANSFER_WRITE 0x1
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#define SPI_ENGINE_TRANSFER_READ 0x2
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#define SPI_ENGINE_CMD(inst, arg1, arg2) \
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(((inst) << 12) | ((arg1) << 8) | (arg2))
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#define SPI_ENGINE_CMD_TRANSFER(flags, n) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, (flags), (n))
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#define SPI_ENGINE_CMD_ASSERT(delay, cs) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, (delay), (cs))
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#define SPI_ENGINE_CMD_WRITE(reg, val) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_WRITE, (reg), (val))
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#define SPI_ENGINE_CMD_SLEEP(delay) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SLEEP, (delay))
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#define SPI_ENGINE_CMD_SYNC(id) \
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SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SYNC, (id))
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struct spi_engine_program {
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unsigned int length;
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uint16_t instructions[];
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};
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struct spi_engine {
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struct clk *clk;
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struct clk *ref_clk;
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spinlock_t lock;
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void __iomem *base;
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struct spi_message *msg;
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struct spi_engine_program *p;
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unsigned cmd_length;
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const uint16_t *cmd_buf;
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struct spi_transfer *tx_xfer;
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unsigned int tx_length;
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const uint8_t *tx_buf;
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struct spi_transfer *rx_xfer;
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unsigned int rx_length;
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uint8_t *rx_buf;
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unsigned int sync_id;
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unsigned int completed_id;
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unsigned int int_enable;
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};
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static void spi_engine_program_add_cmd(struct spi_engine_program *p,
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bool dry, uint16_t cmd)
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{
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if (!dry)
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p->instructions[p->length] = cmd;
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p->length++;
|
||||
}
|
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|
||||
static unsigned int spi_engine_get_config(struct spi_device *spi)
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{
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||||
unsigned int config = 0;
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||||
|
||||
if (spi->mode & SPI_CPOL)
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||||
config |= SPI_ENGINE_CONFIG_CPOL;
|
||||
if (spi->mode & SPI_CPHA)
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||||
config |= SPI_ENGINE_CONFIG_CPHA;
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if (spi->mode & SPI_3WIRE)
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config |= SPI_ENGINE_CONFIG_3WIRE;
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||||
|
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return config;
|
||||
}
|
||||
|
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static unsigned int spi_engine_get_clk_div(struct spi_engine *spi_engine,
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struct spi_device *spi, struct spi_transfer *xfer)
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||||
{
|
||||
unsigned int clk_div;
|
||||
|
||||
clk_div = DIV_ROUND_UP(clk_get_rate(spi_engine->ref_clk),
|
||||
xfer->speed_hz * 2);
|
||||
if (clk_div > 255)
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clk_div = 255;
|
||||
else if (clk_div > 0)
|
||||
clk_div -= 1;
|
||||
|
||||
return clk_div;
|
||||
}
|
||||
|
||||
static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
unsigned int len = xfer->len;
|
||||
|
||||
while (len) {
|
||||
unsigned int n = min(len, 256U);
|
||||
unsigned int flags = 0;
|
||||
|
||||
if (xfer->tx_buf)
|
||||
flags |= SPI_ENGINE_TRANSFER_WRITE;
|
||||
if (xfer->rx_buf)
|
||||
flags |= SPI_ENGINE_TRANSFER_READ;
|
||||
|
||||
spi_engine_program_add_cmd(p, dry,
|
||||
SPI_ENGINE_CMD_TRANSFER(flags, n - 1));
|
||||
len -= n;
|
||||
}
|
||||
}
|
||||
|
||||
static void spi_engine_gen_sleep(struct spi_engine_program *p, bool dry,
|
||||
struct spi_engine *spi_engine, unsigned int clk_div, unsigned int delay)
|
||||
{
|
||||
unsigned int spi_clk = clk_get_rate(spi_engine->ref_clk);
|
||||
unsigned int t;
|
||||
|
||||
if (delay == 0)
|
||||
return;
|
||||
|
||||
t = DIV_ROUND_UP(delay * spi_clk, (clk_div + 1) * 2);
|
||||
while (t) {
|
||||
unsigned int n = min(t, 256U);
|
||||
|
||||
spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_SLEEP(n - 1));
|
||||
t -= n;
|
||||
}
|
||||
}
|
||||
|
||||
static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry,
|
||||
struct spi_device *spi, bool assert)
|
||||
{
|
||||
unsigned int mask = 0xff;
|
||||
|
||||
if (assert)
|
||||
mask ^= BIT(spi->chip_select);
|
||||
|
||||
spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(1, mask));
|
||||
}
|
||||
|
||||
static int spi_engine_compile_message(struct spi_engine *spi_engine,
|
||||
struct spi_message *msg, bool dry, struct spi_engine_program *p)
|
||||
{
|
||||
struct spi_device *spi = msg->spi;
|
||||
struct spi_transfer *xfer;
|
||||
int clk_div, new_clk_div;
|
||||
bool cs_change = true;
|
||||
|
||||
clk_div = -1;
|
||||
|
||||
spi_engine_program_add_cmd(p, dry,
|
||||
SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG,
|
||||
spi_engine_get_config(spi)));
|
||||
|
||||
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
|
||||
new_clk_div = spi_engine_get_clk_div(spi_engine, spi, xfer);
|
||||
if (new_clk_div != clk_div) {
|
||||
clk_div = new_clk_div;
|
||||
spi_engine_program_add_cmd(p, dry,
|
||||
SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV,
|
||||
clk_div));
|
||||
}
|
||||
|
||||
if (cs_change)
|
||||
spi_engine_gen_cs(p, dry, spi, true);
|
||||
|
||||
spi_engine_gen_xfer(p, dry, xfer);
|
||||
spi_engine_gen_sleep(p, dry, spi_engine, clk_div,
|
||||
xfer->delay_usecs);
|
||||
|
||||
cs_change = xfer->cs_change;
|
||||
if (list_is_last(&xfer->transfer_list, &msg->transfers))
|
||||
cs_change = !cs_change;
|
||||
|
||||
if (cs_change)
|
||||
spi_engine_gen_cs(p, dry, spi, false);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void spi_engine_xfer_next(struct spi_engine *spi_engine,
|
||||
struct spi_transfer **_xfer)
|
||||
{
|
||||
struct spi_message *msg = spi_engine->msg;
|
||||
struct spi_transfer *xfer = *_xfer;
|
||||
|
||||
if (!xfer) {
|
||||
xfer = list_first_entry(&msg->transfers,
|
||||
struct spi_transfer, transfer_list);
|
||||
} else if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
|
||||
xfer = NULL;
|
||||
} else {
|
||||
xfer = list_next_entry(xfer, transfer_list);
|
||||
}
|
||||
|
||||
*_xfer = xfer;
|
||||
}
|
||||
|
||||
static void spi_engine_tx_next(struct spi_engine *spi_engine)
|
||||
{
|
||||
struct spi_transfer *xfer = spi_engine->tx_xfer;
|
||||
|
||||
do {
|
||||
spi_engine_xfer_next(spi_engine, &xfer);
|
||||
} while (xfer && !xfer->tx_buf);
|
||||
|
||||
spi_engine->tx_xfer = xfer;
|
||||
if (xfer) {
|
||||
spi_engine->tx_length = xfer->len;
|
||||
spi_engine->tx_buf = xfer->tx_buf;
|
||||
} else {
|
||||
spi_engine->tx_buf = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static void spi_engine_rx_next(struct spi_engine *spi_engine)
|
||||
{
|
||||
struct spi_transfer *xfer = spi_engine->rx_xfer;
|
||||
|
||||
do {
|
||||
spi_engine_xfer_next(spi_engine, &xfer);
|
||||
} while (xfer && !xfer->rx_buf);
|
||||
|
||||
spi_engine->rx_xfer = xfer;
|
||||
if (xfer) {
|
||||
spi_engine->rx_length = xfer->len;
|
||||
spi_engine->rx_buf = xfer->rx_buf;
|
||||
} else {
|
||||
spi_engine->rx_buf = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static bool spi_engine_write_cmd_fifo(struct spi_engine *spi_engine)
|
||||
{
|
||||
void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO;
|
||||
unsigned int n, m, i;
|
||||
const uint16_t *buf;
|
||||
|
||||
n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM);
|
||||
while (n && spi_engine->cmd_length) {
|
||||
m = min(n, spi_engine->cmd_length);
|
||||
buf = spi_engine->cmd_buf;
|
||||
for (i = 0; i < m; i++)
|
||||
writel_relaxed(buf[i], addr);
|
||||
spi_engine->cmd_buf += m;
|
||||
spi_engine->cmd_length -= m;
|
||||
n -= m;
|
||||
}
|
||||
|
||||
return spi_engine->cmd_length != 0;
|
||||
}
|
||||
|
||||
static bool spi_engine_write_tx_fifo(struct spi_engine *spi_engine)
|
||||
{
|
||||
void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO;
|
||||
unsigned int n, m, i;
|
||||
const uint8_t *buf;
|
||||
|
||||
n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM);
|
||||
while (n && spi_engine->tx_length) {
|
||||
m = min(n, spi_engine->tx_length);
|
||||
buf = spi_engine->tx_buf;
|
||||
for (i = 0; i < m; i++)
|
||||
writel_relaxed(buf[i], addr);
|
||||
spi_engine->tx_buf += m;
|
||||
spi_engine->tx_length -= m;
|
||||
n -= m;
|
||||
if (spi_engine->tx_length == 0)
|
||||
spi_engine_tx_next(spi_engine);
|
||||
}
|
||||
|
||||
return spi_engine->tx_length != 0;
|
||||
}
|
||||
|
||||
static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine)
|
||||
{
|
||||
void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO;
|
||||
unsigned int n, m, i;
|
||||
uint8_t *buf;
|
||||
|
||||
n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL);
|
||||
while (n && spi_engine->rx_length) {
|
||||
m = min(n, spi_engine->rx_length);
|
||||
buf = spi_engine->rx_buf;
|
||||
for (i = 0; i < m; i++)
|
||||
buf[i] = readl_relaxed(addr);
|
||||
spi_engine->rx_buf += m;
|
||||
spi_engine->rx_length -= m;
|
||||
n -= m;
|
||||
if (spi_engine->rx_length == 0)
|
||||
spi_engine_rx_next(spi_engine);
|
||||
}
|
||||
|
||||
return spi_engine->rx_length != 0;
|
||||
}
|
||||
|
||||
static irqreturn_t spi_engine_irq(int irq, void *devid)
|
||||
{
|
||||
struct spi_master *master = devid;
|
||||
struct spi_engine *spi_engine = spi_master_get_devdata(master);
|
||||
unsigned int disable_int = 0;
|
||||
unsigned int pending;
|
||||
|
||||
pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
|
||||
|
||||
if (pending & SPI_ENGINE_INT_SYNC) {
|
||||
writel_relaxed(SPI_ENGINE_INT_SYNC,
|
||||
spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
|
||||
spi_engine->completed_id = readl_relaxed(
|
||||
spi_engine->base + SPI_ENGINE_REG_SYNC_ID);
|
||||
}
|
||||
|
||||
spin_lock(&spi_engine->lock);
|
||||
|
||||
if (pending & SPI_ENGINE_INT_CMD_ALMOST_EMPTY) {
|
||||
if (!spi_engine_write_cmd_fifo(spi_engine))
|
||||
disable_int |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
|
||||
}
|
||||
|
||||
if (pending & SPI_ENGINE_INT_SDO_ALMOST_EMPTY) {
|
||||
if (!spi_engine_write_tx_fifo(spi_engine))
|
||||
disable_int |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
|
||||
}
|
||||
|
||||
if (pending & (SPI_ENGINE_INT_SDI_ALMOST_FULL | SPI_ENGINE_INT_SYNC)) {
|
||||
if (!spi_engine_read_rx_fifo(spi_engine))
|
||||
disable_int |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
|
||||
}
|
||||
|
||||
if (pending & SPI_ENGINE_INT_SYNC) {
|
||||
if (spi_engine->msg &&
|
||||
spi_engine->completed_id == spi_engine->sync_id) {
|
||||
struct spi_message *msg = spi_engine->msg;
|
||||
|
||||
kfree(spi_engine->p);
|
||||
msg->status = 0;
|
||||
msg->actual_length = msg->frame_length;
|
||||
spi_engine->msg = NULL;
|
||||
spi_finalize_current_message(master);
|
||||
disable_int |= SPI_ENGINE_INT_SYNC;
|
||||
}
|
||||
}
|
||||
|
||||
if (disable_int) {
|
||||
spi_engine->int_enable &= ~disable_int;
|
||||
writel_relaxed(spi_engine->int_enable,
|
||||
spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
|
||||
}
|
||||
|
||||
spin_unlock(&spi_engine->lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int spi_engine_transfer_one_message(struct spi_master *master,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct spi_engine_program p_dry, *p;
|
||||
struct spi_engine *spi_engine = spi_master_get_devdata(master);
|
||||
unsigned int int_enable = 0;
|
||||
unsigned long flags;
|
||||
size_t size;
|
||||
|
||||
p_dry.length = 0;
|
||||
spi_engine_compile_message(spi_engine, msg, true, &p_dry);
|
||||
|
||||
size = sizeof(*p->instructions) * (p_dry.length + 1);
|
||||
p = kzalloc(sizeof(*p) + size, GFP_KERNEL);
|
||||
if (!p)
|
||||
return -ENOMEM;
|
||||
spi_engine_compile_message(spi_engine, msg, false, p);
|
||||
|
||||
spin_lock_irqsave(&spi_engine->lock, flags);
|
||||
spi_engine->sync_id = (spi_engine->sync_id + 1) & 0xff;
|
||||
spi_engine_program_add_cmd(p, false,
|
||||
SPI_ENGINE_CMD_SYNC(spi_engine->sync_id));
|
||||
|
||||
spi_engine->msg = msg;
|
||||
spi_engine->p = p;
|
||||
|
||||
spi_engine->cmd_buf = p->instructions;
|
||||
spi_engine->cmd_length = p->length;
|
||||
if (spi_engine_write_cmd_fifo(spi_engine))
|
||||
int_enable |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
|
||||
|
||||
spi_engine_tx_next(spi_engine);
|
||||
if (spi_engine_write_tx_fifo(spi_engine))
|
||||
int_enable |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
|
||||
|
||||
spi_engine_rx_next(spi_engine);
|
||||
if (spi_engine->rx_length != 0)
|
||||
int_enable |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
|
||||
|
||||
int_enable |= SPI_ENGINE_INT_SYNC;
|
||||
|
||||
writel_relaxed(int_enable,
|
||||
spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
|
||||
spi_engine->int_enable = int_enable;
|
||||
spin_unlock_irqrestore(&spi_engine->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_engine_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_engine *spi_engine;
|
||||
struct spi_master *master;
|
||||
unsigned int version;
|
||||
struct resource *res;
|
||||
int irq;
|
||||
int ret;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq <= 0)
|
||||
return -ENXIO;
|
||||
|
||||
spi_engine = devm_kzalloc(&pdev->dev, sizeof(*spi_engine), GFP_KERNEL);
|
||||
if (!spi_engine)
|
||||
return -ENOMEM;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, 0);
|
||||
if (!master)
|
||||
return -ENOMEM;
|
||||
|
||||
spi_master_set_devdata(master, spi_engine);
|
||||
|
||||
spin_lock_init(&spi_engine->lock);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
spi_engine->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(spi_engine->base)) {
|
||||
ret = PTR_ERR(spi_engine->base);
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
version = readl(spi_engine->base + SPI_ENGINE_REG_VERSION);
|
||||
if (SPI_ENGINE_VERSION_MAJOR(version) != 1) {
|
||||
dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%c\n",
|
||||
SPI_ENGINE_VERSION_MAJOR(version),
|
||||
SPI_ENGINE_VERSION_MINOR(version),
|
||||
SPI_ENGINE_VERSION_PATCH(version));
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
spi_engine->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
|
||||
if (IS_ERR(spi_engine->clk)) {
|
||||
ret = PTR_ERR(spi_engine->clk);
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
spi_engine->ref_clk = devm_clk_get(&pdev->dev, "spi_clk");
|
||||
if (IS_ERR(spi_engine->ref_clk)) {
|
||||
ret = PTR_ERR(spi_engine->ref_clk);
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(spi_engine->clk);
|
||||
if (ret)
|
||||
goto err_put_master;
|
||||
|
||||
ret = clk_prepare_enable(spi_engine->ref_clk);
|
||||
if (ret)
|
||||
goto err_clk_disable;
|
||||
|
||||
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
|
||||
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
|
||||
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
|
||||
|
||||
ret = request_irq(irq, spi_engine_irq, 0, pdev->name, master);
|
||||
if (ret)
|
||||
goto err_ref_clk_disable;
|
||||
|
||||
master->dev.parent = &pdev->dev;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE;
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
master->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;
|
||||
master->transfer_one_message = spi_engine_transfer_one_message;
|
||||
master->num_chipselect = 8;
|
||||
|
||||
ret = spi_register_master(master);
|
||||
if (ret)
|
||||
goto err_free_irq;
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
|
||||
return 0;
|
||||
err_free_irq:
|
||||
free_irq(irq, master);
|
||||
err_ref_clk_disable:
|
||||
clk_disable_unprepare(spi_engine->ref_clk);
|
||||
err_clk_disable:
|
||||
clk_disable_unprepare(spi_engine->clk);
|
||||
err_put_master:
|
||||
spi_master_put(master);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spi_engine_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct spi_engine *spi_engine = spi_master_get_devdata(master);
|
||||
int irq = platform_get_irq(pdev, 0);
|
||||
|
||||
spi_unregister_master(master);
|
||||
|
||||
free_irq(irq, master);
|
||||
|
||||
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
|
||||
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
|
||||
writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET);
|
||||
|
||||
clk_disable_unprepare(spi_engine->ref_clk);
|
||||
clk_disable_unprepare(spi_engine->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id spi_engine_match_table[] = {
|
||||
{ .compatible = "adi,axi-spi-engine-1.00.a" },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver spi_engine_driver = {
|
||||
.probe = spi_engine_probe,
|
||||
.remove = spi_engine_remove,
|
||||
.driver = {
|
||||
.name = "spi-engine",
|
||||
.of_match_table = spi_engine_match_table,
|
||||
},
|
||||
};
|
||||
module_platform_driver(spi_engine_driver);
|
||||
|
||||
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
||||
MODULE_DESCRIPTION("Analog Devices SPI engine peripheral driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -727,11 +727,6 @@ static int bcm2835_spi_setup(struct spi_device *spi)
|
|||
spi->chip_select, spi->cs_gpio, err);
|
||||
return err;
|
||||
}
|
||||
/* the implementation of pinctrl-bcm2835 currently does not
|
||||
* set the GPIO value when using gpio_direction_output
|
||||
* so we are setting it here explicitly
|
||||
*/
|
||||
gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -64,9 +64,9 @@
|
|||
#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
|
||||
#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000
|
||||
#define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800
|
||||
#define BCM2835_AUX_SPI_CNTL0_CPHA_IN 0x00000400
|
||||
#define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400
|
||||
#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
|
||||
#define BCM2835_AUX_SPI_CNTL0_CPHA_OUT 0x00000100
|
||||
#define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x00000100
|
||||
#define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080
|
||||
#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040
|
||||
#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F
|
||||
|
|
@ -92,9 +92,6 @@
|
|||
#define BCM2835_AUX_SPI_POLLING_LIMIT_US 30
|
||||
#define BCM2835_AUX_SPI_POLLING_JIFFIES 2
|
||||
|
||||
#define BCM2835_AUX_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
|
||||
| SPI_NO_CS)
|
||||
|
||||
struct bcm2835aux_spi {
|
||||
void __iomem *regs;
|
||||
struct clk *clk;
|
||||
|
|
@ -212,9 +209,15 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
|
|||
ret = IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* and if rx_len is 0 then wake up completion and disable spi */
|
||||
if (!bs->tx_len) {
|
||||
/* disable tx fifo empty interrupt */
|
||||
bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
|
||||
BCM2835_AUX_SPI_CNTL1_IDLE);
|
||||
}
|
||||
|
||||
/* and if rx_len is 0 then disable interrupts and wake up completion */
|
||||
if (!bs->rx_len) {
|
||||
bcm2835aux_spi_reset_hw(bs);
|
||||
bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
|
||||
complete(&master->xfer_completion);
|
||||
}
|
||||
|
||||
|
|
@ -307,9 +310,6 @@ static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
|
|||
}
|
||||
}
|
||||
|
||||
/* Transfer complete - reset SPI HW */
|
||||
bcm2835aux_spi_reset_hw(bs);
|
||||
|
||||
/* and return without waiting for completion */
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -330,10 +330,6 @@ static int bcm2835aux_spi_transfer_one(struct spi_master *master,
|
|||
* resulting (potentially) in more interrupts when transferring
|
||||
* more than 12 bytes
|
||||
*/
|
||||
bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
|
||||
BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
|
||||
BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
|
||||
bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
|
||||
|
||||
/* set clock */
|
||||
spi_hz = tfr->speed_hz;
|
||||
|
|
@ -348,17 +344,13 @@ static int bcm2835aux_spi_transfer_one(struct spi_master *master,
|
|||
} else { /* the slowest we can go */
|
||||
speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
|
||||
}
|
||||
/* mask out old speed from previous spi_transfer */
|
||||
bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
|
||||
/* set the new speed */
|
||||
bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
|
||||
|
||||
spi_used_hz = clk_hz / (2 * (speed + 1));
|
||||
|
||||
/* handle all the modes */
|
||||
if (spi->mode & SPI_CPOL)
|
||||
bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
|
||||
if (spi->mode & SPI_CPHA)
|
||||
bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT |
|
||||
BCM2835_AUX_SPI_CNTL0_CPHA_IN;
|
||||
|
||||
/* set transmit buffers and length */
|
||||
bs->tx_buf = tfr->tx_buf;
|
||||
bs->rx_buf = tfr->rx_buf;
|
||||
|
|
@ -382,6 +374,40 @@ static int bcm2835aux_spi_transfer_one(struct spi_master *master,
|
|||
return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
|
||||
}
|
||||
|
||||
static int bcm2835aux_spi_prepare_message(struct spi_master *master,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct spi_device *spi = msg->spi;
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
|
||||
bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
|
||||
BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
|
||||
BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
|
||||
bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
|
||||
|
||||
/* handle all the modes */
|
||||
if (spi->mode & SPI_CPOL) {
|
||||
bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
|
||||
bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
|
||||
} else {
|
||||
bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
|
||||
}
|
||||
bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
|
||||
bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
|
||||
bcm2835aux_spi_reset_hw(bs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bcm2835aux_spi_handle_err(struct spi_master *master,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
|
|
@ -405,11 +431,13 @@ static int bcm2835aux_spi_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
master->mode_bits = BCM2835_AUX_SPI_MODE_BITS;
|
||||
master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
master->num_chipselect = -1;
|
||||
master->transfer_one = bcm2835aux_spi_transfer_one;
|
||||
master->handle_err = bcm2835aux_spi_handle_err;
|
||||
master->prepare_message = bcm2835aux_spi_prepare_message;
|
||||
master->unprepare_message = bcm2835aux_spi_unprepare_message;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
|
||||
bs = spi_master_get_devdata(master);
|
||||
|
|
|
|||
|
|
@ -1589,13 +1589,30 @@ static void of_register_spi_devices(struct spi_master *master) { }
|
|||
static int acpi_spi_add_resource(struct acpi_resource *ares, void *data)
|
||||
{
|
||||
struct spi_device *spi = data;
|
||||
struct spi_master *master = spi->master;
|
||||
|
||||
if (ares->type == ACPI_RESOURCE_TYPE_SERIAL_BUS) {
|
||||
struct acpi_resource_spi_serialbus *sb;
|
||||
|
||||
sb = &ares->data.spi_serial_bus;
|
||||
if (sb->type == ACPI_RESOURCE_SERIAL_TYPE_SPI) {
|
||||
/*
|
||||
* ACPI DeviceSelection numbering is handled by the
|
||||
* host controller driver in Windows and can vary
|
||||
* from driver to driver. In Linux we always expect
|
||||
* 0 .. max - 1 so we need to ask the driver to
|
||||
* translate between the two schemes.
|
||||
*/
|
||||
if (master->fw_translate_cs) {
|
||||
int cs = master->fw_translate_cs(master,
|
||||
sb->device_selection);
|
||||
if (cs < 0)
|
||||
return cs;
|
||||
spi->chip_select = cs;
|
||||
} else {
|
||||
spi->chip_select = sb->device_selection;
|
||||
}
|
||||
|
||||
spi->max_speed_hz = sb->connection_speed;
|
||||
|
||||
if (sb->clock_phase == ACPI_SPI_SECOND_PHASE)
|
||||
|
|
|
|||
|
|
@ -372,6 +372,9 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
|
|||
* @dma_rx: DMA receive channel
|
||||
* @dummy_rx: dummy receive buffer for full-duplex devices
|
||||
* @dummy_tx: dummy transmit buffer for full-duplex devices
|
||||
* @fw_translate_cs: If the boot firmware uses different numbering scheme
|
||||
* what Linux expects, this optional hook can be used to translate
|
||||
* between the two.
|
||||
*
|
||||
* Each SPI master controller can communicate with one or more @spi_device
|
||||
* children. These make a small bus, sharing MOSI, MISO and SCK signals
|
||||
|
|
@ -542,6 +545,8 @@ struct spi_master {
|
|||
/* dummy data for full duplex devices */
|
||||
void *dummy_rx;
|
||||
void *dummy_tx;
|
||||
|
||||
int (*fw_translate_cs)(struct spi_master *master, unsigned cs);
|
||||
};
|
||||
|
||||
static inline void *spi_master_get_devdata(struct spi_master *master)
|
||||
|
|
|
|||
Loading…
Reference in New Issue