docs: perf: convert to ReST
Rename the perf documentation files to ReST, add an index for them and adjust in order to produce a nice html output via the Sphinx build system. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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Mauro Carvalho Chehab
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6baec31591
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@ -1,3 +1,4 @@
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==========================
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ARM Cache Coherent Network
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==========================
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@ -29,6 +30,7 @@ Crosspoint watchpoint-based events (special "event" value 0xfe)
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require "xp" and "vc" as as above plus "port" (device port index),
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"dir" (transmit/receive direction), comparator values ("cmp_l"
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and "cmp_h") and "mask", being index of the comparator mask.
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Masks are defined separately from the event description
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(due to limited number of the config values) in the "cmp_mask"
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directory, with first 8 configurable by user and additional
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@ -44,16 +46,16 @@ request the events on this processor (if not, the perf_event->cpu value
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will be overwritten anyway). In case of this processor being offlined,
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the events are migrated to another one and the attribute is updated.
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Example of perf tool use:
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Example of perf tool use::
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/ # perf list | grep ccn
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ccn/cycles/ [Kernel PMU event]
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<...>
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ccn/xp_valid_flit,xp=?,port=?,vc=?,dir=?/ [Kernel PMU event]
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<...>
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/ # perf list | grep ccn
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ccn/cycles/ [Kernel PMU event]
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<...>
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ccn/xp_valid_flit,xp=?,port=?,vc=?,dir=?/ [Kernel PMU event]
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<...>
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/ # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \
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sleep 1
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/ # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \
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sleep 1
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The driver does not support sampling, therefore "perf record" will
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not work. Per-task (without "-a") perf sessions are not supported.
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@ -1,3 +1,4 @@
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==================================
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ARM DynamIQ Shared Unit (DSU) PMU
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==================================
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@ -13,7 +14,7 @@ PMU doesn't support process specific events and cannot be used in sampling mode.
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The DSU provides a bitmap for a subset of implemented events via hardware
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registers. There is no way for the driver to determine if the other events
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are available or not. Hence the driver exposes only those events advertised
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by the DSU, in "events" directory under :
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by the DSU, in "events" directory under::
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/sys/bus/event_sources/devices/arm_dsu_<N>/
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@ -23,6 +24,6 @@ and use the raw event code for the unlisted events.
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The driver also exposes the CPUs connected to the DSU instance in "associated_cpus".
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e.g usage :
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e.g usage::
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perf stat -a -e arm_dsu_0/cycles/
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@ -1,5 +1,7 @@
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======================================================
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HiSilicon SoC uncore Performance Monitoring Unit (PMU)
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======================================================
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The HiSilicon SoC chip includes various independent system device PMUs
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such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
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independent and have hardware logic to gather statistics and performance
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@ -11,11 +13,13 @@ called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
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two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
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HiSilicon SoC uncore PMU driver
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---------------------------------------
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-------------------------------
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Each device PMU has separate registers for event counting, control and
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interrupt, and the PMU driver shall register perf PMU drivers like L3C,
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HHA and DDRC etc. The available events and configuration options shall
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be described in the sysfs, see :
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be described in the sysfs, see:
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/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
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/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
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The "perf list" command shall list the available events from sysfs.
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@ -24,27 +28,30 @@ Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
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name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
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where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
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module.
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e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
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SCCL ID #3.
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e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
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SCCL ID #1.
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The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
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ID used to count the uncore PMU event.
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Example usage of perf:
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$# perf list
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hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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Example usage of perf::
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$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
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$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
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$# perf list
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hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
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$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
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The current driver does not support sampling. So "perf record" is unsupported.
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Also attach to a task is unsupported as the events are all uncore.
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@ -0,0 +1,16 @@
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:orphan:
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===========================
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Performance monitor support
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===========================
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.. toctree::
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:maxdepth: 1
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hisi-pmu
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qcom_l2_pmu
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qcom_l3_pmu
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arm-ccn
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xgene-pmu
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arm_dsu_pmu
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thunderx2-pmu
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@ -1,3 +1,4 @@
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=====================================================================
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Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)
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=====================================================================
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@ -28,7 +29,7 @@ The driver provides a "cpumask" sysfs attribute which contains a mask
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consisting of one CPU per cluster which will be used to handle all the PMU
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events on that cluster.
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Examples for use with perf:
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Examples for use with perf::
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perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1
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@ -1,3 +1,4 @@
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===========================================================================
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Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
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===========================================================================
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@ -17,7 +18,7 @@ The hardware implements 32bit event counters and has a flat 8bit event space
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exposed via the "event" format attribute. In addition to the 32bit physical
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counters the driver supports virtual 64bit hardware counters by using hardware
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counter chaining. This feature is exposed via the "lc" (long counter) format
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flag. E.g.:
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flag. E.g.::
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perf stat -e l3cache_0_0/read-miss,lc/
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@ -1,3 +1,4 @@
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=============================================================
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Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE)
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=============================================================
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@ -24,18 +25,18 @@ and configuration options under sysfs, see
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The driver does not support sampling, therefore "perf record" will not
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work. Per-task perf sessions are also not supported.
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Examples:
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Examples::
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# perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
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# perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
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# perf stat -a -e \
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uncore_dmc_0/cnt_cycles/,\
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uncore_dmc_0/data_transfers/,\
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uncore_dmc_0/read_txns/,\
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uncore_dmc_0/write_txns/ sleep 1
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# perf stat -a -e \
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uncore_dmc_0/cnt_cycles/,\
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uncore_dmc_0/data_transfers/,\
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uncore_dmc_0/read_txns/,\
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uncore_dmc_0/write_txns/ sleep 1
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# perf stat -a -e \
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uncore_l3c_0/read_request/,\
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uncore_l3c_0/read_hit/,\
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uncore_l3c_0/inv_request/,\
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uncore_l3c_0/inv_hit/ sleep 1
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# perf stat -a -e \
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uncore_l3c_0/read_request/,\
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uncore_l3c_0/read_hit/,\
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uncore_l3c_0/inv_request/,\
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uncore_l3c_0/inv_hit/ sleep 1
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@ -1,3 +1,4 @@
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================================================
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APM X-Gene SoC Performance Monitoring Unit (PMU)
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================================================
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@ -33,7 +34,7 @@ each PMU, please refer to APM X-Gene User Manual.
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Each perf driver also provides a "cpumask" sysfs attribute, which contains a
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single CPU ID of the processor which will be used to handle all the PMU events.
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Example for perf tool use:
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Example for perf tool use::
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/ # perf list | grep -e l3c -e iob -e mcb -e mc
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l3c0/ackq-full/ [Kernel PMU event]
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@ -1155,7 +1155,7 @@ APPLIED MICRO (APM) X-GENE SOC PMU
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M: Khuong Dinh <khuong@os.amperecomputing.com>
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S: Supported
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F: drivers/perf/xgene_pmu.c
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F: Documentation/perf/xgene-pmu.txt
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F: Documentation/perf/xgene-pmu.rst
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F: Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
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APTINA CAMERA SENSOR PLL
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@ -7262,7 +7262,7 @@ M: Shaokun Zhang <zhangshaokun@hisilicon.com>
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W: http://www.hisilicon.com
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S: Supported
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F: drivers/perf/hisilicon
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F: Documentation/perf/hisi-pmu.txt
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F: Documentation/perf/hisi-pmu.rst
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HISILICON ROCE DRIVER
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M: Lijun Ou <oulijun@huawei.com>
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* the slices. User space needs to aggregate to individual counts to provide
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* a global picture.
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*
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* See Documentation/perf/qcom_l3_pmu.txt for more details.
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* See Documentation/perf/qcom_l3_pmu.rst for more details.
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*
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
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*/
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