DT support for 'dma-ranges'and 'dma-coherent' properties with ARM updates
- The 'dma-ranges' helps to take care of few DMAable system memory restrictions by use of dma_pfn_offset which is maintained per device. Arch code then uses it for dma address translations for such cases. We update the dma_pfn_offset accordingly during DT the device creation process. - The 'dma-coherent' property is used to setup arch's coherent dma_ops. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJTajacAAoJEHJsHOdBp5c/780QAJN50zmxyZ7sqA9xGum8MSJl Vjpp1mw3eu7dZ1HoWcpn35l0tOEVpU/wo4ymtt6YYUhD3Po2LZCl3e43h91B/9/B Ih++WZaN+UmpUpp9YJyeS9pkl0wwEqSmJyTBXZrhFhl4o3KNQlHWPGOMJ5CBPaA0 Z03TT1MeOMiCo10xz6JCA/DjPnQz9m5ClxNXLwdP1KOiTDDsv4gtkTZ0UenttIoU DTerJ+GIt1Gzb+P92aGvuc9wgLKacYmH599m6fQcmd9cIG2oMN2Xdxzfqo56v7Sb TGwFcKWYlhPDbDPmcPlidS6j4O+r8cMRwgHLO3r6LHJezCGQOYU8GzN7m6DKt4ww lCIR/k9u4YY/ZiLFeQ+G0Au8T1J6DHdbCI5sciFI53XYT4HMsV1aNpogOim7adC8 4bPRmGCIN03aW+2ynLkFkdnXSBnaAyjt6qlr5zP8owsKDkV7+0WadQqyD2ovQ0FE sBt1HtOUGUsiR/97J4JFBGFxb84zMa6hXhFVUeFbyScCJNm2gkKeRQfiiB4mZi9L NAX/KVGyS6dktJaoLUiKi/p7aqOat3ezD1PrCziq4ceyWbDLag8Bq9H7rtb7vvqC ulHDUPfRy3Z9kmV8+QAznqPJVY1IHXJ18A+YFXF5ktr+5CJ51C8HjVZP3GZKncPC LpA1rRUEwEqsAwnjzcXW =Q7n3 -----END PGP SIGNATURE----- Merge tag 'dt-dma-properties-for-arm' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into devel-stable DT support for 'dma-ranges'and 'dma-coherent' properties with ARM updates - The 'dma-ranges' helps to take care of few DMAable system memory restrictions by use of dma_pfn_offset which is maintained per device. Arch code then uses it for dma address translations for such cases. We update the dma_pfn_offset accordingly during DT the device creation process. - The 'dma-coherent' property is used to setup arch's coherent dma_ops.
This commit is contained in:
commit
6b74f61a47
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@ -58,21 +58,37 @@ static inline int dma_set_mask(struct device *dev, u64 mask)
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#ifndef __arch_pfn_to_dma
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static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
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{
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if (dev)
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pfn -= dev->dma_pfn_offset;
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return (dma_addr_t)__pfn_to_bus(pfn);
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}
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static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
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{
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return __bus_to_pfn(addr);
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unsigned long pfn = __bus_to_pfn(addr);
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if (dev)
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pfn += dev->dma_pfn_offset;
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return pfn;
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}
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static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
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{
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if (dev) {
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unsigned long pfn = dma_to_pfn(dev, addr);
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return phys_to_virt(__pfn_to_phys(pfn));
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}
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return (void *)__bus_to_virt((unsigned long)addr);
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}
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static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
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{
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if (dev)
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return pfn_to_dma(dev, virt_to_pfn(addr));
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return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
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}
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@ -105,6 +121,13 @@ static inline unsigned long dma_max_pfn(struct device *dev)
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}
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#define dma_max_pfn(dev) dma_max_pfn(dev)
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static inline int set_arch_dma_coherent_ops(struct device *dev)
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{
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set_dma_ops(dev, &arm_coherent_dma_ops);
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return 0;
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}
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#define set_arch_dma_coherent_ops(dev) set_arch_dma_coherent_ops(dev)
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static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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unsigned int offset = paddr & ~PAGE_MASK;
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@ -885,7 +885,7 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
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static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
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size_t size, enum dma_data_direction dir)
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{
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unsigned long paddr;
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phys_addr_t paddr;
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dma_cache_maint_page(page, off, size, dir, dmac_map_area);
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@ -901,7 +901,7 @@ static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
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static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
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size_t size, enum dma_data_direction dir)
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{
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unsigned long paddr = page_to_phys(page) + off;
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phys_addr_t paddr = page_to_phys(page) + off;
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/* FIXME: non-speculating: not required */
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/* don't bother invalidating if DMA to device */
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@ -721,3 +721,113 @@ void __iomem *of_iomap(struct device_node *np, int index)
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return ioremap(res.start, resource_size(&res));
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}
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EXPORT_SYMBOL(of_iomap);
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/**
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* of_dma_get_range - Get DMA range info
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* @np: device node to get DMA range info
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* @dma_addr: pointer to store initial DMA address of DMA range
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* @paddr: pointer to store initial CPU address of DMA range
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* @size: pointer to store size of DMA range
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*
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* Look in bottom up direction for the first "dma-ranges" property
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* and parse it.
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* dma-ranges format:
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* DMA addr (dma_addr) : naddr cells
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* CPU addr (phys_addr_t) : pna cells
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* size : nsize cells
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*
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* It returns -ENODEV if "dma-ranges" property was not found
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* for this device in DT.
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*/
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int of_dma_get_range(struct device_node *np, u64 *dma_addr, u64 *paddr, u64 *size)
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{
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struct device_node *node = of_node_get(np);
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const __be32 *ranges = NULL;
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int len, naddr, nsize, pna;
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int ret = 0;
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u64 dmaaddr;
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if (!node)
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return -EINVAL;
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while (1) {
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naddr = of_n_addr_cells(node);
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nsize = of_n_size_cells(node);
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node = of_get_next_parent(node);
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if (!node)
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break;
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ranges = of_get_property(node, "dma-ranges", &len);
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/* Ignore empty ranges, they imply no translation required */
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if (ranges && len > 0)
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break;
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/*
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* At least empty ranges has to be defined for parent node if
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* DMA is supported
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*/
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if (!ranges)
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break;
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}
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if (!ranges) {
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pr_debug("%s: no dma-ranges found for node(%s)\n",
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__func__, np->full_name);
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ret = -ENODEV;
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goto out;
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}
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len /= sizeof(u32);
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pna = of_n_addr_cells(node);
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/* dma-ranges format:
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* DMA addr : naddr cells
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* CPU addr : pna cells
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* size : nsize cells
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*/
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dmaaddr = of_read_number(ranges, naddr);
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*paddr = of_translate_dma_address(np, ranges);
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if (*paddr == OF_BAD_ADDR) {
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pr_err("%s: translation of DMA address(%pad) to CPU address failed node(%s)\n",
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__func__, dma_addr, np->full_name);
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ret = -EINVAL;
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goto out;
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}
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*dma_addr = dmaaddr;
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*size = of_read_number(ranges + naddr + pna, nsize);
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pr_debug("dma_addr(%llx) cpu_addr(%llx) size(%llx)\n",
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*dma_addr, *paddr, *size);
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out:
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of_node_put(node);
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return ret;
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}
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EXPORT_SYMBOL_GPL(of_dma_get_range);
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/**
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* of_dma_is_coherent - Check if device is coherent
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* @np: device node
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*
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* It returns true if "dma-coherent" property was found
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* for this device in DT.
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*/
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bool of_dma_is_coherent(struct device_node *np)
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{
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struct device_node *node = of_node_get(np);
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while (node) {
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if (of_property_read_bool(node, "dma-coherent")) {
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of_node_put(node);
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return true;
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}
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node = of_get_next_parent(node);
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}
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of_node_put(node);
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return false;
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}
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EXPORT_SYMBOL_GPL(of_dma_is_coherent);
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@ -188,6 +188,64 @@ struct platform_device *of_device_alloc(struct device_node *np,
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}
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EXPORT_SYMBOL(of_device_alloc);
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/**
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* of_dma_configure - Setup DMA configuration
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* @dev: Device to apply DMA configuration
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*
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* Try to get devices's DMA configuration from DT and update it
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* accordingly.
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*
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* In case if platform code need to use own special DMA configuration,it
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* can use Platform bus notifier and handle BUS_NOTIFY_ADD_DEVICE event
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* to fix up DMA configuration.
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*/
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static void of_dma_configure(struct platform_device *pdev)
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{
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u64 dma_addr, paddr, size;
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int ret;
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struct device *dev = &pdev->dev;
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#if defined(CONFIG_MICROBLAZE)
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pdev->archdata.dma_mask = 0xffffffffUL;
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#endif
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/*
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* Set default dma-mask to 32 bit. Drivers are expected to setup
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* the correct supported dma_mask.
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*/
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dev->coherent_dma_mask = DMA_BIT_MASK(32);
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/*
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* Set it to coherent_dma_mask by default if the architecture
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* code has not set it.
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*/
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if (!dev->dma_mask)
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dev->dma_mask = &dev->coherent_dma_mask;
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/*
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* if dma-coherent property exist, call arch hook to setup
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* dma coherent operations.
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*/
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if (of_dma_is_coherent(dev->of_node)) {
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set_arch_dma_coherent_ops(dev);
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dev_dbg(dev, "device is dma coherent\n");
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}
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/*
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* if dma-ranges property doesn't exist - just return else
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* setup the dma offset
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*/
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ret = of_dma_get_range(dev->of_node, &dma_addr, &paddr, &size);
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if (ret < 0) {
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dev_dbg(dev, "no dma range information to setup\n");
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return;
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}
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/* DMA ranges found. Calculate and set dma_pfn_offset */
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dev->dma_pfn_offset = PFN_DOWN(paddr - dma_addr);
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dev_dbg(dev, "dma_pfn_offset(%#08lx)\n", dev->dma_pfn_offset);
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}
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/**
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* of_platform_device_create_pdata - Alloc, initialize and register an of_device
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* @np: pointer to node to create device for
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if (!dev)
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return NULL;
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#if defined(CONFIG_MICROBLAZE)
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dev->archdata.dma_mask = 0xffffffffUL;
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#endif
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dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
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if (!dev->dev.dma_mask)
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dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
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of_dma_configure(dev);
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dev->dev.bus = &platform_bus_type;
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dev->dev.platform_data = platform_data;
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@ -685,6 +685,7 @@ struct acpi_dev_node {
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* @coherent_dma_mask: Like dma_mask, but for alloc_coherent mapping as not all
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* hardware supports 64-bit addresses for consistent allocations
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* such descriptors.
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* @dma_pfn_offset: offset of DMA memory range relatively of RAM
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* @dma_parms: A low level driver may set these to teach IOMMU code about
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* segment limitations.
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* @dma_pools: Dma pools (if dma'ble device).
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not all hardware supports
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64 bit addresses for consistent
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allocations such descriptors. */
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unsigned long dma_pfn_offset;
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struct device_dma_parameters *dma_parms;
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@ -123,6 +123,13 @@ static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask)
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extern u64 dma_get_required_mask(struct device *dev);
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#ifndef set_arch_dma_coherent_ops
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static inline int set_arch_dma_coherent_ops(struct device *dev)
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{
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return 0;
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}
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#endif
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static inline unsigned int dma_get_max_seg_size(struct device *dev)
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{
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return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
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@ -63,6 +63,9 @@ extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
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extern struct of_pci_range *of_pci_range_parser_one(
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struct of_pci_range_parser *parser,
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struct of_pci_range *range);
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extern int of_dma_get_range(struct device_node *np, u64 *dma_addr,
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u64 *paddr, u64 *size);
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extern bool of_dma_is_coherent(struct device_node *np);
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#else /* CONFIG_OF_ADDRESS */
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static inline struct device_node *of_find_matching_node_by_address(
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struct device_node *from,
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@ -90,6 +93,17 @@ static inline struct of_pci_range *of_pci_range_parser_one(
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{
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return NULL;
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}
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static inline int of_dma_get_range(struct device_node *np, u64 *dma_addr,
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u64 *paddr, u64 *size)
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{
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return -ENODEV;
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}
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static inline bool of_dma_is_coherent(struct device_node *np)
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{
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return false;
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}
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#endif /* CONFIG_OF_ADDRESS */
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#ifdef CONFIG_OF
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