Serial: UART driver changes for Cavium OCTEON.
Cavium UART implementation is not covered by existing uart_configS. Define a new uart_config (PORT_OCTEON) which is specified by OCTEON platform device registration code. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -279,6 +279,13 @@ static const struct serial8250_config uart_config[] = {
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.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
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.flags = UART_CAP_FIFO,
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},
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[PORT_OCTEON] = {
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.name = "OCTEON",
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.fifo_size = 64,
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.tx_loadsz = 64,
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.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
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.flags = UART_CAP_FIFO,
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},
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};
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#if defined (CONFIG_SERIAL_8250_AU1X00)
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@ -40,7 +40,8 @@
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#define PORT_NS16550A 14
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#define PORT_XSCALE 15
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#define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
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#define PORT_MAX_8250 16 /* max port ID */
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#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
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#define PORT_MAX_8250 17 /* max port ID */
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/*
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* ARM specific type numbers. These are not currently guaranteed
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