staging: brcm80211: moved fullmac definitions from .h to .c files
And deleted unused definitions. Improves code since it makes clear that the definitions are only used by a specific .c file. Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Roland Vossen
Greg Kroah-Hartman
parent
07bc023c16
commit
6aeea40f56
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@ -58,6 +58,13 @@
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/* debugging macros */
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#define SDLX_MSG(x)
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#define SDIOH_CMD_TYPE_NORMAL 0 /* Normal command */
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#define SDIOH_CMD_TYPE_APPEND 1 /* Append command */
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#define SDIOH_CMD_TYPE_CUTTHRU 2 /* Cut-through command */
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#define SDIOH_DATA_PIO 0 /* PIO mode */
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#define SDIOH_DATA_DMA 1 /* DMA mode */
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struct brcmf_sdio_card {
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bool init_success; /* underlying driver successfully attached */
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void *sdioh; /* handler for sdioh */
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@ -178,10 +178,107 @@ struct rte_console {
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#ifndef BRCMF_FIRSTREAD
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#define BRCMF_FIRSTREAD 32
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#endif
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#if !ISPOWEROF2(BRCMF_FIRSTREAD)
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#error BRCMF_FIRSTREAD is not a power of 2!
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#endif
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/* SBSDIO_DEVICE_CTL */
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#define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when
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* receiving CMD53
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*/
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#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is
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* synchronous to the sdio clock
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*/
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#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host
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* except the chipActive (rev 8)
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*/
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#define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put
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* external pads in tri-state; requires
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* sdio bus power cycle to clear (rev 9)
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*/
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#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */
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#define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */
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#define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */
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#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */
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/* SBSDIO_FUNC1_CHIPCLKCSR */
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#define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */
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#define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */
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#define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */
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#define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */
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#define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */
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#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */
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#define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */
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#define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */
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#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
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#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
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#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
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#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
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#define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \
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(alponly ? 1 : SBSDIO_HTAV(regval)))
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/* direct(mapped) cis space */
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#define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */
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#define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */
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#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */
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#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple,
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* link bytes
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*/
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/* intstatus */
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#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
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#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
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#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
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#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
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#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
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#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
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#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
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#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
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#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
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#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
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#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
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#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
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#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
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#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
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#define I_PC (1 << 10) /* descriptor error */
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#define I_PD (1 << 11) /* data error */
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#define I_DE (1 << 12) /* Descriptor protocol Error */
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#define I_RU (1 << 13) /* Receive descriptor Underflow */
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#define I_RO (1 << 14) /* Receive fifo Overflow */
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#define I_XU (1 << 15) /* Transmit fifo Underflow */
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#define I_RI (1 << 16) /* Receive Interrupt */
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#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
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#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
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#define I_XI (1 << 24) /* Transmit Interrupt */
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#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
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#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
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#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
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#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
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#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
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#define I_SRESET (1 << 30) /* CCCR RES interrupt */
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#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
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#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
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#define I_DMA (I_RI | I_XI | I_ERRORS)
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/* corecontrol */
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#define CC_CISRDY (1 << 0) /* CIS Ready */
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#define CC_BPRESEN (1 << 1) /* CCCR RES signal */
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#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
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#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
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#define CC_XMTDATAAVAIL_MODE (1 << 4)
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#define CC_XMTDATAAVAIL_CTRL (1 << 5)
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/* SDA_FRAMECTRL */
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#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
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#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
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#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
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#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
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/* HW frame tag */
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#define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
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/* Total length of frame header for dongle protocol */
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#define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
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#ifdef SDTEST
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@ -70,75 +70,6 @@ extern const uint brcmf_sdio_msglevel;
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#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
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#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */
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/* SBSDIO_SPROM_CS */
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#define SBSDIO_SPROM_IDLE 0
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#define SBSDIO_SPROM_WRITE 1
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#define SBSDIO_SPROM_READ 2
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#define SBSDIO_SPROM_WEN 4
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#define SBSDIO_SPROM_WDS 7
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#define SBSDIO_SPROM_DONE 8
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/* SBSDIO_SPROM_INFO */
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#define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
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#define SROM_BLANK 0x04 /* depreciated in corerev 6 */
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#define SROM_OTP 0x80 /* OTP present */
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/* SBSDIO_CHIP_CTRL */
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#define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu,
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* 1: power on oscillator
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* (for 4318 only)
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*/
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/* SBSDIO_WATERMARK */
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#define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device
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* to wait before sending data to host
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*/
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/* SBSDIO_DEVICE_CTL */
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#define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when
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* receiving CMD53
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*/
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#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is
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* synchronous to the sdio clock
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*/
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#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host
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* except the chipActive (rev 8)
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*/
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#define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put
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* external pads in tri-state; requires
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* sdio bus power cycle to clear (rev 9)
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*/
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#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */
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#define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */
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#define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */
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#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */
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/* SBSDIO_FUNC1_CHIPCLKCSR */
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#define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */
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#define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */
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#define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */
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#define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */
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#define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */
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#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */
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#define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */
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#define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */
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/* In rev8, actual avail bits followed original docs */
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#define SBSDIO_Rev8_HT_AVAIL 0x40
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#define SBSDIO_Rev8_ALP_AVAIL 0x80
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#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
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#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
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#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
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#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
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#define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \
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(alponly ? 1 : SBSDIO_HTAV(regval)))
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/* SBSDIO_FUNC1_SDIOPULLUP */
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#define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */
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#define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */
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#define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */
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#define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */
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#define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */
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/* function 1 OCP space */
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#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */
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#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
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@ -151,166 +82,12 @@ extern const uint brcmf_sdio_msglevel;
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#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
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#define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */
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/* direct(mapped) cis space */
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#define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */
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#define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */
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#define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */
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#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */
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#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple,
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* link bytes
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*/
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/* indirect cis access (in sprom) */
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#define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from
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* 8th byte
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*/
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#define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one
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* data command
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*/
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#define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */
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/* corecontrol */
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#define CC_CISRDY (1 << 0) /* CIS Ready */
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#define CC_BPRESEN (1 << 1) /* CCCR RES signal */
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#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
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#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
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#define CC_XMTDATAAVAIL_MODE (1 << 4)
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#define CC_XMTDATAAVAIL_CTRL (1 << 5)
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/* corestatus */
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#define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */
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#define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */
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#define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */
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#define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */
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#define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */
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#define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */
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#define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */
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/* intstatus */
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#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
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#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
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#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
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#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
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#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
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#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
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#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
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#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
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#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
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#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
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#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
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#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
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#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
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#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
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#define I_PC (1 << 10) /* descriptor error */
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#define I_PD (1 << 11) /* data error */
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#define I_DE (1 << 12) /* Descriptor protocol Error */
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#define I_RU (1 << 13) /* Receive descriptor Underflow */
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#define I_RO (1 << 14) /* Receive fifo Overflow */
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#define I_XU (1 << 15) /* Transmit fifo Underflow */
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#define I_RI (1 << 16) /* Receive Interrupt */
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#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
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#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
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#define I_XI (1 << 24) /* Transmit Interrupt */
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#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
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#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
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#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
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#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
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#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
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#define I_SRESET (1 << 30) /* CCCR RES interrupt */
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#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
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#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
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#define I_DMA (I_RI | I_XI | I_ERRORS)
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/* sbintstatus */
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#define I_SB_SERR (1 << 8) /* Backplane SError (write) */
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#define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */
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#define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */
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/* sdioaccess */
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#define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */
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#define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */
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#define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */
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#define SDA_WRITE 0x01000000 /* Write bit */
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#define SDA_READ 0x00000000 /* Write bit cleared for Read */
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#define SDA_BUSY 0x80000000 /* Busy bit */
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/* sdioaccess-accessible register address spaces */
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#define SDA_CCCR_SPACE 0x000 /* CCCR register space */
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#define SDA_F1_FBR_SPACE 0x100 /* F1 FBR register space */
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#define SDA_F2_FBR_SPACE 0x200 /* F2 FBR register space */
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#define SDA_F1_REG_SPACE 0x300 /* F1 core-specific register space */
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/* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
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#define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */
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#define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */
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#define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */
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#define SDA_DEVICECONTROL 0x009 /* DeviceControl */
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#define SDA_SBADDRLOW 0x00a /* SbAddrLow */
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#define SDA_SBADDRMID 0x00b /* SbAddrMid */
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#define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */
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#define SDA_FRAMECTRL 0x00d /* FrameCtrl */
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#define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */
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#define SDA_SDIOPULLUP 0x00f /* SdioPullUp */
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#define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */
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#define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */
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#define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */
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#define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */
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/* SDA_F2WATERMARK */
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#define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */
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/* SDA_SBADDRLOW */
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#define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */
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/* SDA_SBADDRMID */
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#define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */
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/* SDA_SBADDRHIGH */
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#define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */
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/* SDA_FRAMECTRL */
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||||
#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
|
||||
#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
|
||||
#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
|
||||
#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
|
||||
|
||||
/* pcmciaframectrl */
|
||||
#define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */
|
||||
#define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */
|
||||
|
||||
/* intrcvlazy */
|
||||
#define IRL_TO_MASK 0x00ffffff /* timeout */
|
||||
#define IRL_FC_MASK 0xff000000 /* frame count */
|
||||
#define IRL_FC_SHIFT 24 /* frame count */
|
||||
|
||||
/* rx header flags */
|
||||
#define RXF_CRC 0x0001 /* CRC error detected */
|
||||
#define RXF_WOOS 0x0002 /* write frame out of sync */
|
||||
#define RXF_WF_TERM 0x0004 /* write frame terminated */
|
||||
#define RXF_ABORT 0x0008 /* write frame aborted */
|
||||
#define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT)
|
||||
|
||||
/* HW frame tag */
|
||||
#define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
|
||||
|
||||
#define SDIOH_READ 0 /* Read request */
|
||||
#define SDIOH_WRITE 1 /* Write request */
|
||||
|
||||
#define SDIOH_DATA_FIX 0 /* Fixed addressing */
|
||||
#define SDIOH_DATA_INC 1 /* Incremental addressing */
|
||||
|
||||
#define SDIOH_CMD_TYPE_NORMAL 0 /* Normal command */
|
||||
#define SDIOH_CMD_TYPE_APPEND 1 /* Append command */
|
||||
#define SDIOH_CMD_TYPE_CUTTHRU 2 /* Cut-through command */
|
||||
|
||||
#define SDIOH_DATA_PIO 0 /* PIO mode */
|
||||
#define SDIOH_DATA_DMA 1 /* DMA mode */
|
||||
|
||||
/* internal return code */
|
||||
#define SUCCESS 0
|
||||
#define ERROR 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue