ixgbe: Add support for entering low power link up state
When the device is closing or suspending, call ixgbe_enter_lplu to enter low power link up state on devices that support it. When this is done, prevent the phy from being reset in the ixgbe_down path so that link is present when calling ixgbe_enter_lplu. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Don Skidmore
Jeff Kirsher
parent
67359c3c9f
commit
6ac7439459
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@ -5798,7 +5798,15 @@ static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
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{
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ixgbe_ptp_suspend(adapter);
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ixgbe_down(adapter);
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if (adapter->hw.phy.ops.enter_lplu) {
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adapter->hw.phy.reset_disable = true;
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ixgbe_down(adapter);
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adapter->hw.phy.ops.enter_lplu(&adapter->hw);
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adapter->hw.phy.reset_disable = false;
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} else {
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ixgbe_down(adapter);
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}
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ixgbe_free_irq(adapter);
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ixgbe_free_all_tx_resources(adapter);
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@ -848,6 +848,7 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */
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#define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6 /* Speed Mask */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s H Duplex */
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@ -856,6 +857,24 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB 0x4 /* 1Gb/s */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB 0x6 /* 10Gb/s */
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#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */
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#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
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#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
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#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */
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#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/
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#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
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#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
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#define IXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400
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#define IXGBE_MII_5GBASE_T_ADVERTISE 0x0800
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#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */
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#define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */
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#define IXGBE_MII_RESTART 0x200
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#define IXGBE_MII_AUTONEG_COMPLETE 0x20
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#define IXGBE_MII_AUTONEG_LINK_UP 0x04
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#define IXGBE_MII_AUTONEG_REG 0x0
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/* Management */
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#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
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@ -1305,6 +1324,7 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
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#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */
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#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */
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#define IXGBE_MDIO_AUTO_NEG_VEN_LSC 0x1 /* AUTO_NEG Vendor Tx LSC */
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#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
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@ -1312,7 +1332,8 @@ struct ixgbe_thermal_sensor_data {
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#define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */
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#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */
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#define IXGBE_AUTO_NEG_LP_STATUS 0xE820 /* AUTO NEG Rx LP Status Reg */
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#define IXGBE_AUTO_NEG_LP_1000BASE_CAP 0x8000 /* AUTO NEG Rx LP 1000BaseT */
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#define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */
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#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */
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#define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
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@ -2041,6 +2062,11 @@ enum {
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#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
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#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */
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#define NVM_INIT_CTRL_3 0x38
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#define NVM_INIT_CTRL_3_LPLU 0x8
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#define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40
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#define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100
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#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
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#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
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#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
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@ -3301,6 +3327,7 @@ struct ixgbe_phy_operations {
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s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
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s32 (*check_overtemp)(struct ixgbe_hw *);
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s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
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s32 (*enter_lplu)(struct ixgbe_hw *);
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s32 (*handle_lasi)(struct ixgbe_hw *hw);
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};
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@ -3311,6 +3338,7 @@ struct ixgbe_eeprom_info {
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u16 word_size;
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u16 address_bits;
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u16 word_page_size;
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u16 ctrl_word_3;
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};
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#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
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@ -3466,6 +3494,10 @@ struct ixgbe_info {
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#define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38
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#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
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#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
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#define IXGBE_FUSES0_300MHZ BIT(5)
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#define IXGBE_FUSES0_REV1 BIT(6)
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#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
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#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
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#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
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@ -1458,6 +1458,144 @@ static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
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return ixgbe_enable_lasi_ext_t_x550em(hw);
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}
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/** ixgbe_get_lcd_x550em - Determine lowest common denominator
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* @hw: pointer to hardware structure
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* @lcd_speed: pointer to lowest common link speed
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*
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* Determine lowest common link speed with link partner.
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**/
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static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
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ixgbe_link_speed *lcd_speed)
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{
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u16 an_lp_status;
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s32 status;
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u16 word = hw->eeprom.ctrl_word_3;
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*lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
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status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&an_lp_status);
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if (status)
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return status;
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/* If link partner advertised 1G, return 1G */
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if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
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*lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
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return status;
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}
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/* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
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if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
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(word & NVM_INIT_CTRL_3_D10GMP_PORT0))
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return status;
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/* Link partner not capable of lower speeds, return 10G */
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*lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
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return status;
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}
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/** ixgbe_enter_lplu_x550em - Transition to low power states
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* @hw: pointer to hardware structure
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*
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* Configures Low Power Link Up on transition to low power states
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* (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
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* the X557 PHY immediately prior to entering LPLU.
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**/
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static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
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{
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u16 an_10g_cntl_reg, autoneg_reg, speed;
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s32 status;
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ixgbe_link_speed lcd_speed;
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u32 save_autoneg;
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bool link_up;
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/* SW LPLU not required on later HW revisions. */
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if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
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return 0;
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/* If blocked by MNG FW, then don't restart AN */
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if (ixgbe_check_reset_blocked(hw))
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return 0;
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status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
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if (status)
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return status;
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status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
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&hw->eeprom.ctrl_word_3);
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if (status)
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return status;
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/* If link is down, LPLU disabled in NVM, WoL disabled, or
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* manageability disabled, then force link down by entering
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* low power mode.
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*/
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if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
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!(hw->wol_enabled || ixgbe_mng_present(hw)))
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return ixgbe_set_copper_phy_power(hw, false);
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/* Determine LCD */
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status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
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if (status)
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return status;
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/* If no valid LCD link speed, then force link down and exit. */
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if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
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return ixgbe_set_copper_phy_power(hw, false);
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status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&speed);
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if (status)
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return status;
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/* If no link now, speed is invalid so take link down */
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status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
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if (status)
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return ixgbe_set_copper_phy_power(hw, false);
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/* clear everything but the speed bits */
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speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
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/* If current speed is already LCD, then exit. */
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if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
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(lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
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((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
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(lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
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return status;
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/* Clear AN completed indication */
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status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&autoneg_reg);
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if (status)
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return status;
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status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&an_10g_cntl_reg);
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if (status)
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return status;
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status = hw->phy.ops.read_reg(hw,
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IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&autoneg_reg);
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if (status)
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return status;
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save_autoneg = hw->phy.autoneg_advertised;
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/* Setup link at least common link speed */
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status = hw->mac.ops.setup_link(hw, lcd_speed, false);
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/* restore autoneg from before setting lplu speed */
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hw->phy.autoneg_advertised = save_autoneg;
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return status;
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}
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/** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
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* @hw: pointer to hardware structure
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*
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@ -1528,6 +1666,11 @@ static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
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ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
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}
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/* setup SW LPLU only for first revision */
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if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
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IXGBE_FUSES0_GROUP(0))))
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phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
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phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
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phy->ops.reset = ixgbe_reset_phy_t_X550em;
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break;
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