PCI: rewrite PCI BAR reading code
Factor out the code to read one BAR from the loop in pci_read_bases into a new function, __pci_read_base. The new code is slightly more readable, better commented and removes the ifdef. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Matthew Wilcox
Jesse Barnes
parent
3713907423
commit
6ac665c63d
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@ -163,28 +163,7 @@ static inline unsigned int pci_calc_resource_flags(unsigned int flags)
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return IORESOURCE_MEM;
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}
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/*
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* Find the extent of a PCI decode..
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*/
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static u32 pci_size(u32 base, u32 maxbase, u32 mask)
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{
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u32 size = mask & maxbase; /* Find the significant bits */
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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return size;
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}
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static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
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static u64 pci_size(u64 base, u64 maxbase, u64 mask)
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{
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u64 size = mask & maxbase; /* Find the significant bits */
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if (!size)
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@ -202,117 +181,142 @@ static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
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return size;
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}
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static inline int is_64bit_memory(u32 mask)
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enum pci_bar_type {
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pci_bar_unknown, /* Standard PCI BAR probe */
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pci_bar_io, /* An io port BAR */
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pci_bar_mem32, /* A 32-bit memory BAR */
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pci_bar_mem64, /* A 64-bit memory BAR */
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};
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static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
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{
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if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
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(PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
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return 1;
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return 0;
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if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
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res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
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return pci_bar_io;
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}
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res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
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if (res->flags == PCI_BASE_ADDRESS_MEM_TYPE_64)
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return pci_bar_mem64;
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return pci_bar_mem32;
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}
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/*
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* If the type is not unknown, we assume that the lowest bit is 'enable'.
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* Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
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*/
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static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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struct resource *res, unsigned int pos)
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{
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u32 l, sz, mask;
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mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
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res->name = pci_name(dev);
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pci_read_config_dword(dev, pos, &l);
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pci_write_config_dword(dev, pos, mask);
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pci_read_config_dword(dev, pos, &sz);
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pci_write_config_dword(dev, pos, l);
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/*
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* All bits set in sz means the device isn't working properly.
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* If the BAR isn't implemented, all bits must be 0. If it's a
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* memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
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* 1 must be clear.
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*/
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if (!sz || sz == 0xffffffff)
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goto fail;
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/*
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* I don't know how l can have all bits set. Copied from old code.
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* Maybe it fixes a bug on some ancient platform.
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*/
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if (l == 0xffffffff)
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l = 0;
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if (type == pci_bar_unknown) {
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type = decode_bar(res, l);
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res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
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if (type == pci_bar_io) {
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l &= PCI_BASE_ADDRESS_IO_MASK;
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mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
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} else {
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l &= PCI_BASE_ADDRESS_MEM_MASK;
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mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
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}
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} else {
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res->flags |= (l & IORESOURCE_ROM_ENABLE);
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l &= PCI_ROM_ADDRESS_MASK;
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mask = (u32)PCI_ROM_ADDRESS_MASK;
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}
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if (type == pci_bar_mem64) {
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u64 l64 = l;
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u64 sz64 = sz;
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u64 mask64 = mask | (u64)~0 << 32;
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pci_read_config_dword(dev, pos + 4, &l);
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pci_write_config_dword(dev, pos + 4, ~0);
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pci_read_config_dword(dev, pos + 4, &sz);
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pci_write_config_dword(dev, pos + 4, l);
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l64 |= ((u64)l << 32);
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sz64 |= ((u64)sz << 32);
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sz64 = pci_size(l64, sz64, mask64);
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if (!sz64)
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goto fail;
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if ((BITS_PER_LONG < 64) && (sz64 > 0x100000000ULL)) {
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dev_err(&dev->dev, "can't handle 64-bit BAR\n");
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goto fail;
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} else if ((BITS_PER_LONG < 64) && l) {
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/* Address above 32-bit boundary; disable the BAR */
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pci_write_config_dword(dev, pos, 0);
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pci_write_config_dword(dev, pos + 4, 0);
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res->start = 0;
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res->end = sz64;
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} else {
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res->start = l64;
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res->end = l64 + sz64;
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}
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} else {
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sz = pci_size(l, sz, mask);
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if (!sz)
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goto fail;
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res->start = l;
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res->end = l + sz;
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}
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out:
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return (type == pci_bar_mem64) ? 1 : 0;
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fail:
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res->flags = 0;
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goto out;
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}
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static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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{
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unsigned int pos, reg, next;
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u32 l, sz;
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struct resource *res;
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unsigned int pos, reg;
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for(pos=0; pos<howmany; pos = next) {
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u64 l64;
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u64 sz64;
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u32 raw_sz;
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next = pos+1;
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res = &dev->resource[pos];
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res->name = pci_name(dev);
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for (pos = 0; pos < howmany; pos++) {
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struct resource *res = &dev->resource[pos];
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reg = PCI_BASE_ADDRESS_0 + (pos << 2);
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pci_read_config_dword(dev, reg, &l);
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pci_write_config_dword(dev, reg, ~0);
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pci_read_config_dword(dev, reg, &sz);
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pci_write_config_dword(dev, reg, l);
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if (!sz || sz == 0xffffffff)
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continue;
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if (l == 0xffffffff)
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l = 0;
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raw_sz = sz;
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if ((l & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY) {
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sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
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/*
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* For 64bit prefetchable memory sz could be 0, if the
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* real size is bigger than 4G, so we need to check
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* szhi for that.
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*/
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if (!is_64bit_memory(l) && !sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
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} else {
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sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
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if (!sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_IO_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
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}
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res->end = res->start + (unsigned long) sz;
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res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
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if (is_64bit_memory(l)) {
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u32 szhi, lhi;
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pci_read_config_dword(dev, reg+4, &lhi);
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pci_write_config_dword(dev, reg+4, ~0);
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pci_read_config_dword(dev, reg+4, &szhi);
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pci_write_config_dword(dev, reg+4, lhi);
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sz64 = ((u64)szhi << 32) | raw_sz;
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l64 = ((u64)lhi << 32) | l;
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sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
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next++;
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#if BITS_PER_LONG == 64
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if (!sz64) {
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res->start = 0;
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res->end = 0;
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res->flags = 0;
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continue;
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}
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res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
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res->end = res->start + sz64;
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#else
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if (sz64 > 0x100000000ULL) {
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dev_err(&dev->dev, "BAR %d: can't handle 64-bit"
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" BAR\n", pos);
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res->start = 0;
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res->flags = 0;
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} else if (lhi) {
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/* 64-bit wide address, treat as disabled */
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pci_write_config_dword(dev, reg,
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l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
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pci_write_config_dword(dev, reg+4, 0);
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res->start = 0;
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res->end = sz;
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}
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#endif
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}
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pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
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}
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if (rom) {
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struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
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dev->rom_base_reg = rom;
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res = &dev->resource[PCI_ROM_RESOURCE];
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res->name = pci_name(dev);
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pci_read_config_dword(dev, rom, &l);
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pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
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pci_read_config_dword(dev, rom, &sz);
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pci_write_config_dword(dev, rom, l);
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if (l == 0xffffffff)
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l = 0;
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if (sz && sz != 0xffffffff) {
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sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
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if (sz) {
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res->flags = (l & IORESOURCE_ROM_ENABLE) |
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IORESOURCE_MEM | IORESOURCE_PREFETCH |
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IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
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IORESOURCE_SIZEALIGN;
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res->start = l & PCI_ROM_ADDRESS_MASK;
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res->end = res->start + (unsigned long) sz;
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}
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}
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res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
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IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
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IORESOURCE_SIZEALIGN;
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__pci_read_base(dev, pci_bar_mem32, res, rom);
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}
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}
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