From 4f049e09d833dd9b8c2b0cf7a609d9fc5f9d6348 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 5 Oct 2017 10:58:18 +0200 Subject: [PATCH 01/42] ARM: dts: gr-peach: Fix 'leds' node name indent Fix 'leds' node name indent as it was wrongly aligned. Signed-off-by: Jacopo Mondi Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-gr-peach.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index 13d745bb56a5..a1c5e8823d2b 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -53,7 +53,7 @@ }; }; -leds { + leds { status = "okay"; compatible = "gpio-leds"; From 62cea6d2c6758d6a9513ecf3c70498623d5bf1d2 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 5 Oct 2017 10:58:19 +0200 Subject: [PATCH 02/42] ARM: dts: gr-peach: Enable MTU2 timer pulse unit MTU2 multi-function/multi-channel timer/counter is not enabled for GR-Peach board. The timer is used as clock event source to schedule wake-ups, and without this enabled all sleeps not performed through busy waiting hang the board. Signed-off-by: Jacopo Mondi Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-gr-peach.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index a1c5e8823d2b..9661d43f5236 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -78,6 +78,10 @@ clock-frequency = <48000000>; }; +&mtu2 { + status = "okay"; +}; + &scif2 { pinctrl-names = "default"; pinctrl-0 = <&scif2_pins>; From 9f77b4801944b6c74b871f9252e09177e273212c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 4 Oct 2017 14:36:46 +0200 Subject: [PATCH 03/42] ARM: dts: r8a7790: Use generic node name for VSP1 nodes Use the preferred generic node name instead of the specific name. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 081cf5cdb13b..17a48199b7a9 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1014,7 +1014,7 @@ status = "disabled"; }; - vsp1@fe920000 { + vsp@fe920000 { compatible = "renesas,vsp1"; reg = <0 0xfe920000 0 0x8000>; interrupts = ; @@ -1023,7 +1023,7 @@ resets = <&cpg 130>; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = ; @@ -1032,7 +1032,7 @@ resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = ; @@ -1041,7 +1041,7 @@ resets = <&cpg 128>; }; - vsp1@fe938000 { + vsp@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = ; From 18e5500c1510c844d5c3071f06089b638326bc52 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 4 Oct 2017 14:36:47 +0200 Subject: [PATCH 04/42] ARM: dts: r8a7791: Use generic node name for VSP1 nodes Use the preferred generic node name instead of the specific name. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 5a8a15847076..97bed8253bc3 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1073,7 +1073,7 @@ status = "disabled"; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = ; @@ -1082,7 +1082,7 @@ resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = ; @@ -1091,7 +1091,7 @@ resets = <&cpg 128>; }; - vsp1@fe938000 { + vsp@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = ; From 2ea2e06cdac491cf254ce6221371a6993e7a46fb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 4 Oct 2017 14:36:48 +0200 Subject: [PATCH 05/42] ARM: dts: r8a7792: Use generic node name for VSP1 nodes Use the preferred generic node name instead of the specific name. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index c332f77ebb6b..549eafe8ff12 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -794,7 +794,7 @@ status = "disabled"; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = ; @@ -803,7 +803,7 @@ resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = ; @@ -812,7 +812,7 @@ resets = <&cpg 128>; }; - vsp1@fe938000 { + vsp@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = ; From 8b40ea19233cc53f9d5d33a44d6fc833a765bab2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 4 Oct 2017 14:36:49 +0200 Subject: [PATCH 06/42] ARM: dts: r8a7794: Use generic node name for VSP1 nodes Use the preferred generic node name instead of the specific name. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 035c33715b65..19cff0dd90cf 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -970,7 +970,7 @@ }; }; - vsp1@fe928000 { + vsp@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = ; @@ -979,7 +979,7 @@ resets = <&cpg 131>; }; - vsp1@fe930000 { + vsp@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = ; From 4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 6 Oct 2017 18:59:52 +0100 Subject: [PATCH 07/42] ARM: dts: iwg20d-q7: Rework DT architecture MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the same carrier board may host RZ/G1M and RZ/G1N based Systems on Module, the DT architecture for iwg20d-q7 needs better decoupling. This patch provides: * iwg20d-q7-common.dtsi - its purpose is to define the carrier board definitions, and its content is basically the same as the previous version of r8a7743-iwg20d-q7.dts, only it has no reference to the SoM .dtsi, and that's why the filename doesn't mention the SoC name any more. * r8a7743-iwg20d-q7.dts - its new purpose is to put together the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board .dtsi defined by this very patch, along with "model" and "compatible" properties. The final DT architecture to describe the board is now: r8a7743-iwg20d-q7.dts # Carrier Board + SoM ├── r8a7743-iwg20m.dtsi # SoM │   └── r8a7743.dtsi # SoC └── iwg20d-q7-common.dtsi # Carrier Board and maximizes the reuse of the definitions for the carrier board and for the SoM. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/iwg20d-q7-common.dtsi | 147 ++++++++++++++++++++++++ arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 139 +--------------------- 2 files changed, 149 insertions(+), 137 deletions(-) create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi new file mode 100644 index 000000000000..1c072c0a4888 --- /dev/null +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -0,0 +1,147 @@ +/* + * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + aliases { + serial0 = &scif0; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + }; +}; + +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 0136864bc595..6aa6b7467704 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for the iWave-RZG1M Qseven carrier board + * Device Tree Source for the iWave-RZ/G1M Qseven board * * Copyright (C) 2017 Renesas Electronics Corp. * @@ -10,144 +10,9 @@ /dts-v1/; #include "r8a7743-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" / { model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M"; compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; - - aliases { - serial0 = &scif0; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; -}; - -&pfc { - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - avb_pins: avb { - groups = "avb_mdio", "avb_gmii"; - function = "avb"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - reg = <3>; - micrel,led-mode = <1>; - }; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@68 { - compatible = "ti,bq32000"; - reg = <0x68>; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; }; From 2ee18841ff649e973d62afc6096b892396a676ef Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 6 Oct 2017 18:59:53 +0100 Subject: [PATCH 08/42] ARM: dts: iwg20d-q7-dbcm-ca: Add device trees for camera DB This patch adds a .dtsi that describes the camera daughter board and a .dts to describe the HW made of iWave's RZ/G1M SoM, iWave's RZ/G1M/G1N Qseven carrier board, and the camera daughter board. The camera daughter board .dtsi adds support for ttySC[14]. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi | 43 +++++++++++++++++++ .../boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts | 19 ++++++++ 3 files changed, 63 insertions(+) create mode 100644 arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e87f311ee9f2..8c34d06cfda0 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -724,6 +724,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ r8a7743-iwg20d-q7.dtb \ + r8a7743-iwg20d-q7-dbcm-ca.dtb \ r8a7743-sk-rzg1m.dtb \ r8a7745-iwg22d-sodimm.dtb \ r8a7745-sk-rzg1e.dtb \ diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi new file mode 100644 index 000000000000..31fab5f183a9 --- /dev/null +++ b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi @@ -0,0 +1,43 @@ +/* + * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + aliases { + serial1 = &scif1; + serial4 = &hscif1; + }; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&pfc { + hscif1_pins: hscif1 { + groups = "hscif1_data_c", "hscif1_ctrl_c"; + function = "hscif1"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_d"; + function = "scif1"; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts new file mode 100644 index 000000000000..d90eb8464222 --- /dev/null +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts @@ -0,0 +1,19 @@ +/* + * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7743-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" +#include "iwg20d-q7-dbcm-ca.dtsi" + +/ { + model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board"; + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; +}; From 5bdc81259bb0efd5bd71820ef15757b70beae751 Mon Sep 17 00:00:00 2001 From: Dietmar Eggemann Date: Wed, 30 Aug 2017 15:41:20 +0100 Subject: [PATCH 09/42] ARM: dts: r8a7790: add cpu capacity-dmips-mhz information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platform is affected once cpu-invariant accounting support is re-connected to the task scheduler: r8a7790-lager Signed-off-by: Dietmar Eggemann Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 17a48199b7a9..92b7f3bd8b69 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -56,6 +56,7 @@ clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -73,6 +74,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -82,6 +84,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu3: cpu@3 { @@ -91,6 +94,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu4: cpu@100 { @@ -100,6 +104,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu5: cpu@101 { @@ -109,6 +114,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu6: cpu@102 { @@ -118,6 +124,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu7: cpu@103 { @@ -127,6 +134,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; L2_CA15: cache-controller-0 { From ab290a32925e6f7db9e71546098077b3e72cc617 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 9 Oct 2017 14:58:57 +0100 Subject: [PATCH 10/42] ARM: dts: r8a7745: Add internal PCI bridge nodes Add device nodes for the r8a7745 internal PCI bridge devices. Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 46 ++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 6ba3b8b04edb..b4e9536a84d6 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -845,6 +845,52 @@ resets = <&cpg 311>; status = "disabled"; }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7745", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7745", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + }; }; /* External root clock */ From 237173a4bbf4c0710dbb7c35a4e2763671d293df Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 9 Oct 2017 14:58:58 +0100 Subject: [PATCH 11/42] ARM: dts: r8a7745: Add USB PHY DT support Define the r8a7745 generic part of the USB PHY device node. Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index b4e9536a84d6..17cfa53f3c76 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -891,6 +891,28 @@ 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7745", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; }; /* External root clock */ From c3e35873e37b77581be942b7284e705e997014fc Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 9 Oct 2017 14:58:59 +0100 Subject: [PATCH 12/42] ARM: dts: r8a7745: Link PCI USB devices to USB PHY Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device. Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 17cfa53f3c76..3a50f703601c 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -867,6 +867,18 @@ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; }; pci1: pci@ee0d0000 { @@ -890,6 +902,18 @@ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; }; usbphy: usb-phy@e6590100 { From bc058f6f03e47610c994a97ecf3bf8a3ea44efee Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 9 Oct 2017 14:59:00 +0100 Subject: [PATCH 13/42] ARM: dts: iwg22d-sodimm: Enable internal PCI Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index 8772c561e3a8..e378e5ecfcac 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -55,6 +55,11 @@ function = "sdhi0"; power-source = <3300>; }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; }; &scif4 { @@ -92,3 +97,9 @@ cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; From aea3c9d9726148331d874c2b91aeb663430099d7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 9 Oct 2017 14:59:01 +0100 Subject: [PATCH 14/42] ARM: dts: iwg22d-sodimm: Enable USB PHY Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index e378e5ecfcac..52153ec3638c 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -103,3 +103,7 @@ pinctrl-0 = <&usb1_pins>; pinctrl-names = "default"; }; + +&usbphy { + status = "okay"; +}; From 4b4a3b1c33b7a389d90624683d8f1a8d1dc2affa Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 9 Oct 2017 14:21:18 +0100 Subject: [PATCH 15/42] ARM: dts: r8a7743: Add HS-USB device node Define the R8A7743 generic part of the HS-USB device node. It is up to the board file to enable the device. Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index d541fd9ffafb..080eff9bb3c3 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -945,6 +945,20 @@ status = "disabled"; }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7743", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + usbphy: usb-phy@e6590100 { compatible = "renesas,usb-phy-r8a7743", "renesas,rcar-gen2-usb-phy"; From 405b580227ff1ae8fde82a666a2a5c0391a7e64a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 11 Oct 2017 10:04:33 +0100 Subject: [PATCH 16/42] ARM: dts: iwg20d-q7: Enable HS-USB Enable HS-USB device for the iWave G20D-Q7 carrier board based on RZ/G1M. Also disable the host mode support on usb otg port by default to avoid pin conflicts. Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/iwg20d-q7-common.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi index 1c072c0a4888..efd8af9242d1 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -58,6 +58,12 @@ }; }; +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; @@ -72,7 +78,6 @@ }; &pci0 { - status = "okay"; pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; }; From 310861003a0d59cb410538bcdf73a218157a111d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 9 Oct 2017 14:21:20 +0100 Subject: [PATCH 17/42] ARM: dts: r8a7743: Add USB-DMAC device nodes Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 080eff9bb3c3..de89295ce63a 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -355,6 +355,34 @@ dma-channels = <15>; }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7743-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7743-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + /* The memory map in the User's Manual maps the cores to bus * numbers */ From e0a10e7b070624965f20205c59fb2a0c0b465782 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 9 Oct 2017 14:21:21 +0100 Subject: [PATCH 18/42] ARM: dts: r8a7743: Enable DMA for HSUSB This patch adds DMA properties to the HSUSB node. Signed-off-by: Biju Das Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index de89295ce63a..699c04003eac 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -979,6 +979,9 @@ reg = <0 0xe6590000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; resets = <&cpg 704>; renesas,buswait = <4>; From 349adfbf27269bad4fa6915e77c97a06487266a5 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Mon, 9 Oct 2017 10:48:34 +0200 Subject: [PATCH 19/42] ARM: dts: gr-peach: Add ETHER pin group Add pin configuration subnode for ETHER pin group. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-gr-peach.dts | 39 +++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index 9661d43f5236..eca14e3801ec 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -68,6 +68,28 @@ /* P6_2 as RxD2; P6_3 as TxD2 */ pinmux = , ; }; + + ether_pins: ether { + /* Ethernet on Ports 1,3,5,10 */ + pinmux = , /* P1_14 = ET_COL */ + , /* P3_0 = ET_TXCLK */ + , /* P3_3 = ET_MDIO */ + , /* P3_4 = ET_RXCLK */ + , /* P3_5 = ET_RXER */ + , /* P3_6 = ET_RXDV */ + , /* P5_9 = ET_MDC */ + , /* P10_1 = ET_TXER */ + , /* P10_2 = ET_TXEN */ + , /* P10_3 = ET_CRS */ + , /* P10_4 = ET_TXD0 */ + , /* P10_5 = ET_TXD1 */ + , /* P10_6 = ET_TXD2 */ + , /* P10_7 = ET_TXD3 */ + , /* P10_8 = ET_RXD0 */ + , /* P10_9 = ET_RXD1 */ + ,/* P10_10 = ET_RXD2 */ + ;/* P10_11 = ET_RXD3 */ + }; }; &extal_clk { @@ -88,3 +110,20 @@ status = "okay"; }; + +ðer { + pinctrl-names = "default"; + pinctrl-0 = <ðer_pins>; + + status = "okay"; + + renesas,no-ether-link; + phy-handle = <&phy0>; + + phy0: ethernet-phy@0 { + reg = <0>; + + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <5>; + }; +}; From 1126e108a3ad8ae92a0532259e3da4b14072355f Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Mon, 9 Oct 2017 10:48:35 +0200 Subject: [PATCH 20/42] ARM: dts: gr-peach: Enable ostm0 and ostm1 timers Enable ostm0 and ostm1 timers to be used as clock source and clockevent source. The timers provides greater accuracy than the already enabled mtu2 one. With these enabled: clocksource: ostm: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 57352151442 ns sched_clock: 32 bits at 33MHz, resolution 30ns, wraps every 64440619504ns ostm: used for clocksource ostm: used for clock events Signed-off-by: Jacopo Mondi Suggested-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-gr-peach.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index eca14e3801ec..779f724b4531 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -104,6 +104,14 @@ status = "okay"; }; +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + &scif2 { pinctrl-names = "default"; pinctrl-0 = <&scif2_pins>; From 9b43ba66f145127025cf82a35f47f228ea936935 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 13 Oct 2017 14:33:02 +0200 Subject: [PATCH 21/42] ARM: dts: r8a7778: Use R-Car GPIO Gen1 fallback compat string Use newly added R-Car GPIO Gen1 fallback compat string in place of now deprecated non-generation specific R-Car GPIO fallback compat string in DT of r8a7778 SoC. As the driver does not match on "renesas,gpio-r8a7778" there are some run-time considerations for this patch: * When a resulting DTB is used with kernels newer than v4.14 this should not have any run-time effect as renesas,rcar-gen1-gpio is matched by the driver since commit dbd1dad2ab8f ("gpio: rcar: add gen[123] fallback compatibility strings") * However, when used with older kernels GPIO will be disabled as no compat string match will be made by the driver. The regression documented above for the new DTB with old kernel case is acceptable in my opinion. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7778.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 8f3156c0e575..a31817b2dda7 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -88,7 +88,7 @@ }; gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc40000 0x2c>; interrupts = ; #gpio-cells = <2>; @@ -99,7 +99,7 @@ }; gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc41000 0x2c>; interrupts = ; #gpio-cells = <2>; @@ -110,7 +110,7 @@ }; gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc42000 0x2c>; interrupts = ; #gpio-cells = <2>; @@ -121,7 +121,7 @@ }; gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc43000 0x2c>; interrupts = ; #gpio-cells = <2>; @@ -132,7 +132,7 @@ }; gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio"; reg = <0xffc44000 0x2c>; interrupts = ; #gpio-cells = <2>; From 88cb141b84ca665110ef36db76294453b83486df Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 13 Oct 2017 14:33:03 +0200 Subject: [PATCH 22/42] ARM: dts: r8a7779: Use R-Car GPIO Gen1 fallback compat string Use newly added R-Car GPIO Gen1 fallback compat string in place of now deprecated non-generation specific R-Car GPIO fallback compat string in DT of r8a7779 SoC. As the driver does not match on "renesas,gpio-r8a7779" there are some run-time considerations for this patch: * When a resulting DTB is used with kernels newer than v4.14 this should not have any run-time effect as renesas,rcar-gen1-gpio is matched by the driver since commit dbd1dad2ab8f ("gpio: rcar: add gen[123] fallback compatibility strings") * However, when used with older kernels GPIO will be disabled as no compat string match will be made by the driver. The regression documented above for the new DTB with old kernel case is acceptable in my opinion. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7779.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 8ee0b2ca5d39..ccef2cfab6e0 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -76,7 +76,7 @@ }; gpio0: gpio@ffc40000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc40000 0x2c>; interrupts = ; #gpio-cells = <2>; @@ -87,7 +87,7 @@ }; gpio1: gpio@ffc41000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc41000 0x2c>; interrupts = ; #gpio-cells = <2>; @@ -98,7 +98,7 @@ }; gpio2: gpio@ffc42000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc42000 0x2c>; interrupts = ; #gpio-cells = <2>; @@ -109,7 +109,7 @@ }; gpio3: gpio@ffc43000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc43000 0x2c>; interrupts = ; #gpio-cells = <2>; @@ -120,7 +120,7 @@ }; gpio4: gpio@ffc44000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc44000 0x2c>; interrupts = ; #gpio-cells = <2>; @@ -131,7 +131,7 @@ }; gpio5: gpio@ffc45000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc45000 0x2c>; interrupts = ; #gpio-cells = <2>; @@ -142,7 +142,7 @@ }; gpio6: gpio@ffc46000 { - compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; reg = <0xffc46000 0x2c>; interrupts = ; #gpio-cells = <2>; From 936e7d7472547294fa305f60546afad232896fdc Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 13 Oct 2017 14:33:04 +0200 Subject: [PATCH 23/42] ARM: dts: r8a7743: Use R-Car GPIO Gen2 fallback compat string Use newly added R-Car GPIO Gen2 fallback compat string in place of now deprecated non-generation specific R-Car GPIO fallback compat string in the DT of the r8a7743 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before considering the fallback compat string. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7743.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 699c04003eac..f29f15d4d659 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -108,7 +108,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -123,7 +123,7 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -138,7 +138,7 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -153,7 +153,7 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -168,7 +168,7 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -183,7 +183,7 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -198,7 +198,7 @@ gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -213,7 +213,7 @@ gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a7743", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = ; #gpio-cells = <2>; From 26742a192c82cc28723c80dbecc5976db0508461 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 13 Oct 2017 14:33:05 +0200 Subject: [PATCH 24/42] ARM: dts: r8a7790: Use R-Car GPIO Gen2 fallback compat string Use newly added R-Car GPIO Gen2 fallback compat string in place of now deprecated non-generation specific R-Car GPIO fallback compat string in the DT of the r8a7790 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before considering the fallback compat string. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7790.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 92b7f3bd8b69..f247beb3863f 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -200,7 +200,7 @@ }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -214,7 +214,7 @@ }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -228,7 +228,7 @@ }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -242,7 +242,7 @@ }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -256,7 +256,7 @@ }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -270,7 +270,7 @@ }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = ; #gpio-cells = <2>; From 7140383d59fc590b9f52e4133e8454603c76bb78 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 13 Oct 2017 14:33:06 +0200 Subject: [PATCH 25/42] ARM: dts: r8a7791: Use R-Car GPIO Gen2 fallback compat string Use newly added R-Car GPIO Gen2 fallback compat string in place of now deprecated non-generation specific R-Car GPIO fallback compat string in the DT of the r8a7791 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before considering the fallback compat string. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 97bed8253bc3..3c7b919efa48 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -124,7 +124,7 @@ }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -138,7 +138,7 @@ }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -152,7 +152,7 @@ }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -166,7 +166,7 @@ }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -180,7 +180,7 @@ }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -194,7 +194,7 @@ }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -208,7 +208,7 @@ }; gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -222,7 +222,7 @@ }; gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = ; #gpio-cells = <2>; From 7f4a16c4143a99ca4520c565abb07a4fffbae0ff Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 13 Oct 2017 14:33:07 +0200 Subject: [PATCH 26/42] ARM: dts: r8a7792: Use R-Car GPIO Gen2 fallback compat string Use newly added R-Car GPIO Gen2 fallback compat string in place of now deprecated non-generation specific R-Car GPIO fallback compat string in the DT of the r8a7792 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before considering the fallback compat string. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7792.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 549eafe8ff12..56570d1ce5f6 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -147,7 +147,7 @@ gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -162,7 +162,7 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -177,7 +177,7 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -192,7 +192,7 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -207,7 +207,7 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -222,7 +222,7 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -237,7 +237,7 @@ gpio6: gpio@e6055100 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055100 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -252,7 +252,7 @@ gpio7: gpio@e6055200 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055200 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -267,7 +267,7 @@ gpio8: gpio@e6055300 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055300 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -282,7 +282,7 @@ gpio9: gpio@e6055400 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -297,7 +297,7 @@ gpio10: gpio@e6055500 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055500 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -312,7 +312,7 @@ gpio11: gpio@e6055600 { compatible = "renesas,gpio-r8a7792", - "renesas,gpio-rcar"; + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055600 0 0x50>; interrupts = ; #gpio-cells = <2>; From c37417dca041d76a66a78012f93e9a3c879706c4 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 13 Oct 2017 14:33:08 +0200 Subject: [PATCH 27/42] ARM: dts: r8a7793: Use R-Car GPIO Gen2 fallback compat string Use newly added R-Car GPIO Gen2 fallback compat string in place of now deprecated non-generation specific R-Car GPIO fallback compat string in the DT of the r8a7793 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before considering the fallback compat string. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7793.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index aa19b93494bf..76418c375a10 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -115,7 +115,7 @@ }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -129,7 +129,7 @@ }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -143,7 +143,7 @@ }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -157,7 +157,7 @@ }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -171,7 +171,7 @@ }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -185,7 +185,7 @@ }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -199,7 +199,7 @@ }; gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -213,7 +213,7 @@ }; gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = ; #gpio-cells = <2>; From 7ee06c8a0b3a1fad3d9660da00e895aaf784fdee Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Fri, 13 Oct 2017 14:33:09 +0200 Subject: [PATCH 28/42] ARM: dts: r8a7794: Use R-Car GPIO Gen2 fallback compat string Use newly added R-Car GPIO Gen2 fallback compat string in place of now deprecated non-generation specific R-Car GPIO fallback compat string in the DT of the r8a7794 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before considering the fallback compat string. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 19cff0dd90cf..7720a6ca8702 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -82,7 +82,7 @@ }; gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -96,7 +96,7 @@ }; gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -110,7 +110,7 @@ }; gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -124,7 +124,7 @@ }; gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -138,7 +138,7 @@ }; gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -152,7 +152,7 @@ }; gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -166,7 +166,7 @@ }; gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; + compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = ; #gpio-cells = <2>; From a7869a5bc82682ac31452e178b4b3e9f8b48e7df Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:06 +0200 Subject: [PATCH 29/42] ARM: dts: r8a73a4: Add clock for CA15 CPU0 core Improve hardware description by adding a clocks property to the device node corresponding to the primary CA15 CPU core, which is for now the only one described. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 310222634570..dd4d09712a2a 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -27,6 +27,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; clock-frequency = <1500000000>; power-domains = <&pd_a2sl>; next-level-cache = <&L2_CA15>; From a60ddf507dda0ede43b72d348283d8725a5a83c7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:07 +0200 Subject: [PATCH 30/42] ARM: dts: r8a7743: Add missing clock for secondary CA15 CPU core Currently only the primary CPU in the CA15 cluster has a clocks property, while the secondary CPU core is driven by the same clock. Add the missing clocks property to fix this. Signed-off-by: Geert Uytterhoeven Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index f29f15d4d659..4db4f61be25a 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -63,6 +63,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; power-domains = <&sysc R8A7743_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; From d3e865a35a4f8cee0d0b86d7cd6d05908f01a874 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:08 +0200 Subject: [PATCH 31/42] ARM: dts: r8a7778: Add clock for CA9 CPU core Improve hardware description by adding a clock property to the device node corresponding to the CA9 CPU core. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index a31817b2dda7..a39472aab867 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -33,6 +33,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <800000000>; + clocks = <&z_clk>; }; }; From fa9f95a3d1bf827e7b83310e5e5c83f36382e25f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:09 +0200 Subject: [PATCH 32/42] ARM: dts: r8a7779: Add clocks for CA9 CPU cores Improve hardware description by adding clocks properties to the device nodes corresponding to the CA9 CPU cores. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index ccef2cfab6e0..e8eb94748b27 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -29,12 +29,14 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; power-domains = <&sysc R8A7779_PD_ARM1>; }; cpu@2 { @@ -42,6 +44,7 @@ compatible = "arm,cortex-a9"; reg = <2>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; power-domains = <&sysc R8A7779_PD_ARM2>; }; cpu@3 { @@ -49,6 +52,7 @@ compatible = "arm,cortex-a9"; reg = <3>; clock-frequency = <1000000000>; + clocks = <&cpg_clocks R8A7779_CLK_Z>; power-domains = <&sysc R8A7779_PD_ARM3>; }; }; From aa4c2fdf495f000fa9ae57c073c0c4575c21983e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:10 +0200 Subject: [PATCH 33/42] ARM: dts: r8a7790: Add missing clocks for secondary CA15 CPU cores Currently only the primary CPU in the CA15 cluster has a clocks property, while the secondary CPU cores are driven by the same clock. Add the missing clocks properties to fix this. Signed-off-by: Geert Uytterhoeven Tested-by: Simon Horman Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index f247beb3863f..e85eb42f97e8 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -72,6 +72,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; @@ -82,6 +83,7 @@ compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; @@ -92,6 +94,7 @@ compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; From aea0089ae8058a9bf4c9766f3208809fc28c99f0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:11 +0200 Subject: [PATCH 34/42] ARM: dts: r8a7790: Add clocks for CA7 CPU cores Currently only the CPU cores in the CA15 cluster have clocks properties. Add the missing clocks properties for the CPU cores in the CA7 cluster to fix this. Signed-off-by: Geert Uytterhoeven Tested-by: Simon Horman Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index e85eb42f97e8..2f017fee4009 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -105,6 +105,7 @@ compatible = "arm,cortex-a7"; reg = <0x100>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; @@ -115,6 +116,7 @@ compatible = "arm,cortex-a7"; reg = <0x101>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; @@ -125,6 +127,7 @@ compatible = "arm,cortex-a7"; reg = <0x102>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; @@ -135,6 +138,7 @@ compatible = "arm,cortex-a7"; reg = <0x103>; clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; From 60b672fe7e28358c1cffdab4724b203f6cf2901b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:12 +0200 Subject: [PATCH 35/42] ARM: dts: r8a7791: Add missing clock for secondary CA15 CPU core Currently only the primary CPU in the CA15 cluster has a clocks property, while the secondary CPU core is driven by the same clock. Add the missing clocks property to fix this. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 3c7b919efa48..67831d0405f3 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -70,6 +70,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; From 8684a24caa3d59d9ba03f1e6f9653b49ac78ec04 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:13 +0200 Subject: [PATCH 36/42] ARM: dts: r8a7792: Add missing clock for secondary CA15 CPU core Currently only the primary CPU in the CA15 cluster has a clocks property, while the secondary CPU core is driven by the same clock. Add the missing clocks property to fix this. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 56570d1ce5f6..131f65b0426e 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -56,6 +56,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; power-domains = <&sysc R8A7792_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; From f359fd3bba71176a122939fe3db9c7f20000d3f0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:14 +0200 Subject: [PATCH 37/42] ARM: dts: r8a7793: Add missing clock for secondary CA15 CPU core Currently only the primary CPU in the CA15 cluster has a clocks property, while the secondary CPU core is driven by the same clock. Add the missing clocks property to fix this. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 76418c375a10..58eae569b4e0 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -62,6 +62,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>; }; From 5614e69269232da1f378e5be92714b96cdb090ef Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:15 +0200 Subject: [PATCH 38/42] ARM: dts: r8a7794: Add missing clock for secondary CA7 CPU core Currently only the primary CPU in the CA7 cluster has a clocks property, while the secondary CPU core is driven by the same clock. Add the missing clocks property to fix this. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 7720a6ca8702..905e50c9b524 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -53,6 +53,7 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; }; From e5042d0b97be6a831f9f204f3574d73b3f947fa5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:16 +0200 Subject: [PATCH 39/42] ARM: dts: sh73a0: Add clocks for CA9 CPU cores Improve hardware description by adding clocks properties to the device nodes corresponding to the CA9 CPU cores. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 4ea5c5a16c57..88d7e5631d34 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -27,6 +27,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <1196000000>; + clocks = <&cpg_clocks SH73A0_CLK_Z>; power-domains = <&pd_a2sl>; next-level-cache = <&L2>; }; @@ -35,6 +36,7 @@ compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1196000000>; + clocks = <&cpg_clocks SH73A0_CLK_Z>; power-domains = <&pd_a2sl>; next-level-cache = <&L2>; }; From 44842cc8a89aa7742bc47737aa75da5910aa5f33 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:04 +0200 Subject: [PATCH 40/42] dt-bindings: clk: r7s72100: Add missing I and G clocks Add the missing definitions for the I (CPU) and G (Image Processing) clocks, so these clocks can be referred to from device nodes in DT. Note that these clocks are already fully supported otherwise (DT bindings, Linux driver, r7s72100.dtsi), they were just omitted from the header file. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- include/dt-bindings/clock/r7s72100-clock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h index 7dd8bc0c3cd0..0dcb3e87d44c 100644 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ b/include/dt-bindings/clock/r7s72100-clock.h @@ -11,6 +11,8 @@ #define __DT_BINDINGS_CLOCK_R7S72100_H__ #define R7S72100_CLK_PLL 0 +#define R7S72100_CLK_I 1 +#define R7S72100_CLK_G 2 /* MSTP2 */ #define R7S72100_CLK_CORESIGHT 0 From f20d89ac0fefad2465e6ce6d64e9ff82e33889dd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Oct 2017 11:35:05 +0200 Subject: [PATCH 41/42] ARM: dts: r7s72100: Add clock for CA9 CPU core Improve hardware description by adding a clock property to the device node corresponding to the CA9 CPU core. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 4ed12a4d9d51..ab9645a42eca 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -203,6 +203,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + clocks = <&cpg_clocks R7S72100_CLK_I>; next-level-cache = <&L2>; }; }; From b6d3b649441936621c87b79bff8dd436e2397e3c Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 16 Oct 2017 11:12:49 +0100 Subject: [PATCH 42/42] ARM: dts: r8a7743: Add xhci support to SoC dtsi Add node for xhci. Boards DT files will enable it if needed. Signed-off-by: Fabrizio Castro Reviewed-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 4db4f61be25a..7bbba4a36f31 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -932,6 +932,26 @@ status = "disabled"; }; + /* + * pci1 and xhci share the same phy, therefore only one of them + * can be active at any one time. If both of them are enabled, + * a race condition will determine who'll control the phy. + * A firmware file is needed by the xhci driver in order for + * USB 3.0 to work properly. + */ + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7743", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7743"; reg = <0 0xee100000 0 0x328>;