From 20a2742e5784295b9197250b50c40f6d38a55880 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 13 Dec 2017 16:36:47 -0800 Subject: [PATCH 1/3] dt-bindings: ti-sysc: Update binding for timers and capabilities MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ti-sysc binding does not yet describe the capabilities of the interconnect target module. So to make the ti-sysc binding usable for configuring the interconnect target module, we need to add few more properties: 1. To detect between omap2 and omap4 timers, let's add compatibles for them for "ti,sysc-omap2-timer" and,sysc-omap4-timer". This makes it easier to pick up the already initialized system timers later on 2. Let's add "ti,sysc-mask" for a mask of features supported by the interconnect target module. This describes what we have available in the various SYSCONFIG registers 3. Let's add "ti,sysc-midle" and "ti,sysc-sidle" lists for the master and slave idle modes supported by the interconnect target module. These describe the values available for MIDLE and SIDLE bits in the SYSCONFIG registers 4. Some interconnect target modules need a short delay after reset before they can be accessed, let's use "ti,sysc-delay-us" for that 5. Let's add "ti,syss-mask" bit to describe the optional SYSSTATUS register bits for reset done bits 6. Let's support the two existing custom quirk properties already listed in Documentation/devicetree/bindings/arm/omap/omap.txt for "ti,no-reset-on-init" and "ti,no-idle-on-init" 7. And finally, let's add a header for the binding for the dts files and the driver to use Cc: Benoît Cousson Cc: Dave Gerlach Cc: Laurent Pinchart Cc: Liam Girdwood Cc: Mark Brown Cc: Mark Rutland Cc: Mauro Carvalho Chehab Cc: Nishanth Menon Cc: Matthijs van Duin Cc: Paul Walmsley Cc: Peter Ujfalusi Cc: Sakari Ailus Cc: Suman Anna Cc: Tero Kristo Cc: Tomi Valkeinen Reviewed-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/bus/ti-sysc.txt | 36 +++++++++++++++++++ include/dt-bindings/bus/ti-sysc.h | 22 ++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 include/dt-bindings/bus/ti-sysc.h diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt index fb1790e39398..48bbb0c96835 100644 --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt +++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt @@ -26,6 +26,8 @@ Required standard properties: or one of the following derivative types for hardware needing special workarounds: + "ti,sysc-omap2-timer" + "ti,sysc-omap4-timer" "ti,sysc-omap3430-sr" "ti,sysc-omap3630-sr" "ti,sysc-omap4-sr" @@ -49,6 +51,26 @@ Required standard properties: Optional properties: +- ti,sysc-mask shall contain mask of supported register bits for the + SYSCONFIG register as documented in the Technical Reference + Manual (TRM) for the interconnect target module + +- ti,sysc-midle list of master idle modes supported by the interconnect + target module as documented in the TRM for SYSCONFIG + register MIDLEMODE bits + +- ti,sysc-sidle list of slave idle modes supported by the interconnect + target module as documented in the TRM for SYSCONFIG + register SIDLEMODE bits + +- ti,sysc-delay-us delay needed after OCP softreset before accssing + SYSCONFIG register again + +- ti,syss-mask optional mask of reset done status bits as described in the + TRM for SYSSTATUS registers, typically 1 with some devices + having separate reset done bits for children like OHCI and + EHCI + - clocks clock specifier for each name in the clock-names as specified in the binding documentation for ti-clkctrl, typically available for all interconnect targets on TI SoCs @@ -61,6 +83,9 @@ Optional properties: - ti,hwmods optional TI interconnect module name to use legacy hwmod platform data +- ti,no-reset-on-init interconnect target module should not be reset at init + +- ti,no-idle-on-init interconnect target module should not be idled at init Example: Single instance of MUSB controller on omap4 using interconnect ranges using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): @@ -74,6 +99,17 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): reg-names = "rev", "sysc", "syss"; clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; clock-names = "fck"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2b000 0x1000>; diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h new file mode 100644 index 000000000000..2c005376ac0e --- /dev/null +++ b/include/dt-bindings/bus/ti-sysc.h @@ -0,0 +1,22 @@ +/* TI sysc interconnect target module defines */ + +/* Generic sysc found on omap2 and later, also known as type1 */ +#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8) +#define SYSC_OMAP2_EMUFREE (1 << 5) +#define SYSC_OMAP2_ENAWAKEUP (1 << 2) +#define SYSC_OMAP2_SOFTRESET (1 << 1) +#define SYSC_OMAP2_AUTOIDLE (1 << 0) + +/* Generic sysc found on omap4 and later, also known as type2 */ +#define SYSC_OMAP4_DMADISABLE (1 << 16) +#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */ +#define SYSC_OMAP4_SOFTRESET (1 << 0) + +/* SmartReflex sysc found on 36xx and later */ +#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) + +/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ +#define SYSC_IDLE_FORCE 0 +#define SYSC_IDLE_NO 1 +#define SYSC_IDLE_SMART 2 +#define SYSC_IDLE_SMART_WKUP 3 From 7d9bfdac31d77305a28531033e604264ae3e449c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 10 Jan 2018 10:14:15 -0800 Subject: [PATCH 2/3] ARM: dts: Fix smartreflex compatible for omap3 shared mpu-iva instance The smartreflex instance for mpu and iva is shared. Let's fix this as I've already gotten confused myself few times wondering where the mpu instance is. Note that we are still probing the driver using platform data so this change is safe to do. Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/power/ti-smartreflex.txt | 2 +- arch/arm/boot/dts/omap3.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/ti-smartreflex.txt b/Documentation/devicetree/bindings/power/ti-smartreflex.txt index 9780957c9115..21ef14d6af12 100644 --- a/Documentation/devicetree/bindings/power/ti-smartreflex.txt +++ b/Documentation/devicetree/bindings/power/ti-smartreflex.txt @@ -7,7 +7,7 @@ Required properties: compatible: Shall be one of the following: "ti,omap3-smartreflex-core" - "ti,omap3-smartreflex-iva" + "ti,omap3-smartreflex-mpu-iva" "ti,omap4-smartreflex-core" "ti,omap4-smartreflex-mpu" "ti,omap4-smartreflex-iva" diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 90b5c7148feb..a5c2440c7051 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -595,7 +595,7 @@ }; smartreflex_mpu_iva: smartreflex@480c9000 { - compatible = "ti,omap3-smartreflex-iva"; + compatible = "ti,omap3-smartreflex-mpu-iva"; ti,hwmods = "smartreflex_mpu_iva"; reg = <0x480c9000 0x400>; interrupts = <18>; From e14d7e5320ebae9bffe4fbd585dfdd9d6de2550f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 11 Jan 2018 16:04:03 -0800 Subject: [PATCH 3/3] ARM: dts: Update ti-sysc data for existing users Let's update the existing users with features and clock data as specified in the binding. This is currently the smartreflex for most part, and also few omap4 modules with no child device driver like mcasp, abe iss and gfx. Note that we had few mistakes that did not get noticed as we're still probing the SmartReflex driver with legacy platform data and using "ti,hwmods" legacy property for ti-sysc driver. So let's fix the omap4 and dra7 smartreflex registers as there is no no revision register. And on omap4, the mcasp module has a revision register according to the TRM. And for omap34xx we need a different configuration compared to 36xx. And the smartreflex on 3517 we've always kept disabled so let's remove any references to it. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517.dtsi | 4 -- arch/arm/boot/dts/dra7.dtsi | 26 ++++++-- arch/arm/boot/dts/omap3.dtsi | 14 ----- arch/arm/boot/dts/omap34xx.dtsi | 39 ++++++++++++ arch/arm/boot/dts/omap36xx.dtsi | 46 ++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 104 ++++++++++++++++++++++++++++---- 6 files changed, 198 insertions(+), 35 deletions(-) diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index 00da3f2c4072..0f0117b72e14 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -99,9 +99,5 @@ status = "disabled"; }; -&smartreflex_mpu_iva { - status = "disabled"; -}; - /include/ "am35xx-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index a1d7178a3966..2b0a541f7f1d 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -7,6 +7,8 @@ * Based on "omap4.dtsi" */ +#include +#include #include #include #include @@ -1514,9 +1516,15 @@ target-module@4a0dd000 { compatible = "ti,sysc-omap4-sr"; ti,hwmods = "smartreflex_core"; - reg = <0x4a0dd000 0x4>, - <0x4a0dd008 0x4>; - reg-names = "rev", "sysc"; + reg = <0x4a0dd038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x4a0dd000 0x001000>; @@ -1527,9 +1535,15 @@ target-module@4a0d9000 { compatible = "ti,sysc-omap4-sr"; ti,hwmods = "smartreflex_mpu"; - reg = <0x4a0d9000 0x4>, - <0x4a0d9008 0x4>; - reg-names = "rev", "sysc"; + reg = <0x4a0d9038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x4a0d9000 0x001000>; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index a5c2440c7051..2ce18785594f 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -587,20 +587,6 @@ dma-names = "rx"; }; - smartreflex_core: smartreflex@480cb000 { - compatible = "ti,omap3-smartreflex-core"; - ti,hwmods = "smartreflex_core"; - reg = <0x480cb000 0x400>; - interrupts = <19>; - }; - - smartreflex_mpu_iva: smartreflex@480c9000 { - compatible = "ti,omap3-smartreflex-mpu-iva"; - ti,hwmods = "smartreflex_mpu_iva"; - reg = <0x480c9000 0x400>; - interrupts = <18>; - }; - timer1: timer@48318000 { compatible = "ti,omap3430-timer"; reg = <0x48318000 0x400>; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index ac4f8795b756..f572a477f74c 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include #include #include "omap3.dtsi" @@ -61,6 +62,44 @@ compatible = "ti,omap34xx-bandgap"; #thermal-sensor-cells = <0>; }; + + target-module@480cb000 { + compatible = "ti,sysc-omap3430-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0x480cb024 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + clocks = <&sr2_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480cb000 0x001000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap3-smartreflex-core"; + reg = <0 0x400>; + interrupts = <19>; + }; + }; + + target-module@480c9000 { + compatible = "ti,sysc-omap3430-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu_iva"; + reg = <0x480c9024 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + clocks = <&sr1_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480c9000 0x001000>; + + smartreflex_mpu_iva: smartreflex@480c9000 { + compatible = "ti,omap3-smartreflex-mpu-iva"; + reg = <0 0x400>; + interrupts = <18>; + }; + }; }; thermal_zones: thermal-zones { diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index ade31d74c70c..6fb23ada1f64 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include #include #include "omap3.dtsi" @@ -93,6 +94,51 @@ compatible = "ti,omap36xx-bandgap"; #thermal-sensor-cells = <0>; }; + + target-module@480cb000 { + compatible = "ti,sysc-omap3630-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0x480cb038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + clocks = <&sr2_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480cb000 0x001000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap3-smartreflex-core"; + reg = <0 0x400>; + interrupts = <19>; + }; + }; + + target-module@480c9000 { + compatible = "ti,sysc-omap3630-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu_iva"; + reg = <0x480c9038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + clocks = <&sr1_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480c9000 0x001000>; + + + smartreflex_mpu_iva: smartreflex@480c9000 { + compatible = "ti,omap3-smartreflex-mpu-iva"; + reg = <0 0x400>; + interrupts = <18>; + }; + }; }; thermal_zones: thermal-zones { diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index e912639c998a..6425902f7ae7 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -6,6 +6,8 @@ * published by the Free Software Foundation. */ +#include +#include #include #include #include @@ -398,6 +400,13 @@ reg = <0x48076000 0x4>, <0x48076010 0x4>; reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x48076000 0x001000>; @@ -468,9 +477,15 @@ target-module@4a0db000 { compatible = "ti,sysc-sr"; ti,hwmods = "smartreflex_iva"; - reg = <0x4a0db000 0x4>, - <0x4a0db008 0x4>; - reg-names = "rev", "sysc"; + reg = <0x4a0db038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x4a0db000 0x001000>; @@ -485,9 +500,15 @@ target-module@4a0dd000 { compatible = "ti,sysc-sr"; ti,hwmods = "smartreflex_core"; - reg = <0x4a0dd000 0x4>, - <0x4a0dd008 0x4>; - reg-names = "rev", "sysc"; + reg = <0x4a0dd038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x4a0dd000 0x001000>; @@ -502,9 +523,15 @@ target-module@4a0d9000 { compatible = "ti,sysc-sr"; ti,hwmods = "smartreflex_mpu"; - reg = <0x4a0d9000 0x4>, - <0x4a0d9008 0x4>; - reg-names = "rev", "sysc"; + reg = <0x4a0d9038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x4a0d9000 0x001000>; @@ -725,6 +752,18 @@ reg = <0x52000000 0x4>, <0x52000010 0x4>; reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,sysc-delay-us = <2>; + clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x52000000 0x1000000>; @@ -829,8 +868,15 @@ target-module@40128000 { compatible = "ti,sysc-mcasp"; ti,hwmods = "mcasp"; - reg = <0x40128004 0x4>; - reg-names = "sysc"; + reg = <0x40128000 0x4>, + <0x40128004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x40128000 0x1000>, /* MPU */ @@ -850,6 +896,13 @@ reg = <0x4012c000 0x4>, <0x4012c010 0x4>; reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ @@ -864,6 +917,15 @@ reg = <0x401f1000 0x4>, <0x401f1010 0x4>; reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */ @@ -970,6 +1032,16 @@ reg = <0x4a10a000 0x4>, <0x4a10a010 0x4>; reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,sysc-delay-us = <2>; + clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x4a10a000 0x1000>; @@ -1200,6 +1272,16 @@ reg = <0x5601fc00 0x4>, <0x5601fc10 0x4>; reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x2000000>;