media: ccs-pll: Remove parallel bus support
The parallel bus PLL calculation has no users. Remove it. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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@ -435,11 +435,6 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
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op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2
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* (pll->csi2.lanes / lane_op_clock_ratio);
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break;
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case CCS_PLL_BUS_TYPE_PARALLEL:
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op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
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/ DIV_ROUND_UP(pll->bits_per_pixel,
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pll->parallel.bus_width);
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break;
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default:
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return -EINVAL;
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}
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@ -13,8 +13,7 @@
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#define CCS_PLL_H
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/* CSI-2 or CCP-2 */
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#define CCS_PLL_BUS_TYPE_CSI2 0x00
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#define CCS_PLL_BUS_TYPE_PARALLEL 0x01
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#define CCS_PLL_BUS_TYPE_CSI2 0x00
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/* op pix clock is for all lanes in total normally */
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#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
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@ -37,14 +36,9 @@ struct ccs_pll_branch_bk {
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struct ccs_pll {
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/* input values */
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uint8_t bus_type;
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union {
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struct {
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uint8_t lanes;
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} csi2;
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struct {
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uint8_t bus_width;
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} parallel;
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};
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struct {
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uint8_t lanes;
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} csi2;
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unsigned long flags;
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uint8_t binning_horizontal;
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uint8_t binning_vertical;
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