Merge branch 'remotes/lorenzo/pci/dwc'
- Constify histb dw_pcie_host_ops structure (Julia Lawall) - Support multiple power domains for imx6 (Leonard Crestez) - Constify layerscape driver data (Stefan Agner) - Update imx6 Kconfig to allow imx6 PCIe in imx7 kernel (Trent Piepho) - Support armada8k GPIO reset (Baruch Siach) - Support suspend/resume support on imx6 (Leonard Crestez) - Don't hard-code DesignWare DBI/ATU offst (Stephen Warren) - Skip i.MX6 PHY setup on i.MX7D (Andrey Smirnov) - Remove Jianguo Sun from HiSilicon STB maintainers (Lorenzo Pieralisi) * remotes/lorenzo/pci/dwc: MAINTAINERS: Remove Jianguo Sun from HiSilicon STB DWC entry PCI: dwc: Don't hard-code DBI/ATU offset PCI: imx: Add imx6sx suspend/resume support PCI: armada8k: Add support for gpio controlled reset signal PCI: dwc: Adjust Kconfig to allow IMX6 PCIe host on IMX7 PCI: dwc: layerscape: Constify driver data PCI: imx: Add multi-pd support dt-bindings: imx6q-pcie: Add multi-pd bindings for imx6sx PCI: histb: Constify dw_pcie_host_ops structure
This commit is contained in:
Bjorn Helgaas
commit
6a790bf0ea
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@ -41,7 +41,9 @@ Optional properties:
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Additional required properties for imx6sx-pcie:
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- clock names: Must include the following additional entries:
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- "pcie_inbound_axi"
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- power-domains: Must be set to a phandle pointing to the PCIE_PHY power domain
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- power-domains: Must be set to phandles pointing to the DISPLAY and
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PCIE_PHY power domains
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- power-domain-names: Must be "pcie", "pcie_phy"
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Additional required properties for imx7d-pcie:
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- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
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@ -11549,7 +11549,6 @@ F: Documentation/devicetree/bindings/pci/kirin-pcie.txt
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F: drivers/pci/controller/dwc/pcie-kirin.c
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PCIE DRIVER FOR HISILICON STB
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M: Jianguo Sun <sunjianguo1@huawei.com>
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M: Shawn Guo <shawn.guo@linaro.org>
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L: linux-pci@vger.kernel.org
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S: Maintained
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@ -89,8 +89,8 @@ config PCI_EXYNOS
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select PCIE_DW_HOST
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config PCI_IMX6
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bool "Freescale i.MX6 PCIe controller"
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depends on SOC_IMX6Q || (ARM && COMPILE_TEST)
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bool "Freescale i.MX6/7 PCIe controller"
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depends on SOC_IMX6Q || SOC_IMX7D || (ARM && COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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@ -27,6 +27,8 @@
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/reset.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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#include "pcie-designware.h"
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@ -59,6 +61,11 @@ struct imx6_pcie {
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u32 tx_swing_low;
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int link_gen;
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struct regulator *vpcie;
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/* power domain for pcie */
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struct device *pd_pcie;
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/* power domain for pcie phy */
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struct device *pd_pcie_phy;
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};
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/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
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@ -292,6 +299,43 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
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return 1;
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}
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static int imx6_pcie_attach_pd(struct device *dev)
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{
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struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
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struct device_link *link;
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/* Do nothing when in a single power domain */
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if (dev->pm_domain)
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return 0;
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imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
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if (IS_ERR(imx6_pcie->pd_pcie))
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return PTR_ERR(imx6_pcie->pd_pcie);
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link = device_link_add(dev, imx6_pcie->pd_pcie,
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DL_FLAG_STATELESS |
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DL_FLAG_PM_RUNTIME |
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DL_FLAG_RPM_ACTIVE);
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if (!link) {
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dev_err(dev, "Failed to add device_link to pcie pd.\n");
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return -EINVAL;
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}
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imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
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if (IS_ERR(imx6_pcie->pd_pcie_phy))
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return PTR_ERR(imx6_pcie->pd_pcie_phy);
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device_link_add(dev, imx6_pcie->pd_pcie_phy,
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DL_FLAG_STATELESS |
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DL_FLAG_PM_RUNTIME |
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DL_FLAG_RPM_ACTIVE);
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if (IS_ERR(link)) {
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dev_err(dev, "Failed to add device_link to pcie_phy pd: %ld\n", PTR_ERR(link));
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return PTR_ERR(link);
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}
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return 0;
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}
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static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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{
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struct device *dev = imx6_pcie->pci->dev;
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@ -773,8 +817,28 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
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static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
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{
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reset_control_assert(imx6_pcie->turnoff_reset);
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reset_control_deassert(imx6_pcie->turnoff_reset);
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struct device *dev = imx6_pcie->pci->dev;
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/* Some variants have a turnoff reset in DT */
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if (imx6_pcie->turnoff_reset) {
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reset_control_assert(imx6_pcie->turnoff_reset);
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reset_control_deassert(imx6_pcie->turnoff_reset);
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goto pm_turnoff_sleep;
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}
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/* Others poke directly at IOMUXC registers */
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switch (imx6_pcie->variant) {
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case IMX6SX:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_PM_TURN_OFF,
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IMX6SX_GPR12_PCIE_PM_TURN_OFF);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
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break;
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default:
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dev_err(dev, "PME_Turn_Off not implemented\n");
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return;
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}
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/*
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* Components with an upstream port must respond to
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@ -783,6 +847,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
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* The standard recommends a 1-10ms timeout after which to
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* proceed anyway as if acks were received.
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*/
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pm_turnoff_sleep:
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usleep_range(1000, 10000);
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}
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@ -792,18 +857,31 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
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clk_disable_unprepare(imx6_pcie->pcie_phy);
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clk_disable_unprepare(imx6_pcie->pcie_bus);
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if (imx6_pcie->variant == IMX7D) {
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switch (imx6_pcie->variant) {
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case IMX6SX:
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clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
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break;
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case IMX7D:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
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break;
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default:
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break;
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}
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}
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static inline bool imx6_pcie_supports_suspend(struct imx6_pcie *imx6_pcie)
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{
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return (imx6_pcie->variant == IMX7D ||
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imx6_pcie->variant == IMX6SX);
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}
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static int imx6_pcie_suspend_noirq(struct device *dev)
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{
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struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
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if (imx6_pcie->variant != IMX7D)
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if (!imx6_pcie_supports_suspend(imx6_pcie))
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return 0;
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imx6_pcie_pm_turnoff(imx6_pcie);
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@ -819,7 +897,7 @@ static int imx6_pcie_resume_noirq(struct device *dev)
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struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
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struct pcie_port *pp = &imx6_pcie->pci->pp;
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if (imx6_pcie->variant != IMX7D)
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if (!imx6_pcie_supports_suspend(imx6_pcie))
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return 0;
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imx6_pcie_assert_core_reset(imx6_pcie);
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@ -985,6 +1063,10 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, imx6_pcie);
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ret = imx6_pcie_attach_pd(dev);
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if (ret)
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return ret;
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ret = imx6_add_pcie_port(imx6_pcie, pdev);
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if (ret < 0)
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return ret;
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@ -222,12 +222,12 @@ static const struct dw_pcie_ops dw_ls_pcie_ops = {
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.link_up = ls_pcie_link_up,
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};
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static struct ls_pcie_drvdata ls1021_drvdata = {
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static const struct ls_pcie_drvdata ls1021_drvdata = {
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.ops = &ls1021_pcie_host_ops,
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.dw_pcie_ops = &dw_ls1021_pcie_ops,
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};
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static struct ls_pcie_drvdata ls1043_drvdata = {
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static const struct ls_pcie_drvdata ls1043_drvdata = {
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.lut_offset = 0x10000,
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.ltssm_shift = 24,
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.lut_dbg = 0x7fc,
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@ -235,7 +235,7 @@ static struct ls_pcie_drvdata ls1043_drvdata = {
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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static struct ls_pcie_drvdata ls1046_drvdata = {
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static const struct ls_pcie_drvdata ls1046_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 24,
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.lut_dbg = 0x407fc,
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@ -243,7 +243,7 @@ static struct ls_pcie_drvdata ls1046_drvdata = {
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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static struct ls_pcie_drvdata ls2080_drvdata = {
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static const struct ls_pcie_drvdata ls2080_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 0,
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.lut_dbg = 0x7fc,
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@ -251,7 +251,7 @@ static struct ls_pcie_drvdata ls2080_drvdata = {
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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static struct ls_pcie_drvdata ls2088_drvdata = {
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static const struct ls_pcie_drvdata ls2088_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 0,
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.lut_dbg = 0x407fc,
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@ -22,6 +22,7 @@
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#include <linux/resource.h>
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
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#include <linux/gpio/consumer.h>
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#include "pcie-designware.h"
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@ -29,6 +30,7 @@ struct armada8k_pcie {
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struct dw_pcie *pci;
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struct clk *clk;
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struct clk *clk_reg;
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struct gpio_desc *reset_gpio;
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};
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#define PCIE_VENDOR_REGS_OFFSET 0x8000
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@ -137,6 +139,12 @@ static int armada8k_pcie_host_init(struct pcie_port *pp)
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct armada8k_pcie *pcie = to_armada8k_pcie(pci);
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if (pcie->reset_gpio) {
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/* assert and then deassert the reset signal */
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gpiod_set_value_cansleep(pcie->reset_gpio, 1);
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msleep(100);
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gpiod_set_value_cansleep(pcie->reset_gpio, 0);
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}
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dw_pcie_setup_rc(pp);
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armada8k_pcie_establish_link(pcie);
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@ -249,6 +257,14 @@ static int armada8k_pcie_probe(struct platform_device *pdev)
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goto fail_clkreg;
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}
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/* Get reset gpio signal and hold asserted (logically high) */
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pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset",
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GPIOD_OUT_HIGH);
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if (IS_ERR(pcie->reset_gpio)) {
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ret = PTR_ERR(pcie->reset_gpio);
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goto fail_clkreg;
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}
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platform_set_drvdata(pdev, pcie);
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ret = armada8k_add_pcie_port(pcie, pdev);
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@ -504,6 +504,10 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
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dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
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return -EINVAL;
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}
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if (pci->iatu_unroll_enabled && !pci->atu_base) {
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dev_err(dev, "atu_base is not populated\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
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if (ret < 0) {
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@ -699,6 +699,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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dev_dbg(pci->dev, "iATU unroll: %s\n",
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pci->iatu_unroll_enabled ? "enabled" : "disabled");
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if (pci->iatu_unroll_enabled && !pci->atu_base)
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pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
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dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_MEM, pp->mem_base,
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pp->mem_bus_addr, pp->mem_size);
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|
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@ -93,7 +93,7 @@ static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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return dw_pcie_readl_dbi(pci, offset + reg);
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return dw_pcie_readl_atu(pci, offset + reg);
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}
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static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
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@ -101,7 +101,7 @@ static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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dw_pcie_writel_dbi(pci, offset + reg, val);
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dw_pcie_writel_atu(pci, offset + reg, val);
|
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}
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|
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static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
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@ -187,7 +187,7 @@ static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
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|
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return dw_pcie_readl_dbi(pci, offset + reg);
|
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return dw_pcie_readl_atu(pci, offset + reg);
|
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}
|
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|
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static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
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|
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@ -195,7 +195,7 @@ static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
|
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{
|
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u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
|
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|
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dw_pcie_writel_dbi(pci, offset + reg, val);
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dw_pcie_writel_atu(pci, offset + reg, val);
|
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}
|
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|
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static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
|
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|
|
|
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|
|
@ -92,12 +92,20 @@
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#define PCIE_ATU_UNR_LOWER_TARGET 0x14
|
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#define PCIE_ATU_UNR_UPPER_TARGET 0x18
|
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|
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/* Register address builder */
|
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#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
|
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((0x3 << 20) | ((region) << 9))
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/*
|
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* The default address offset between dbi_base and atu_base. Root controller
|
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* drivers are not required to initialize atu_base if the offset matches this
|
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* default; the driver core automatically derives atu_base from dbi_base using
|
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* this offset, if atu_base not set.
|
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*/
|
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#define DEFAULT_DBI_ATU_OFFSET (0x3 << 20)
|
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|
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#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
|
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((0x3 << 20) | ((region) << 9) | (0x1 << 8))
|
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/* Register address builder */
|
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#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
|
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((region) << 9)
|
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|
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#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
|
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(((region) << 9) | (0x1 << 8))
|
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|
||||
#define MAX_MSI_IRQS 256
|
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#define MAX_MSI_IRQS_PER_CTRL 32
|
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|
|
@ -219,6 +227,8 @@ struct dw_pcie {
|
|||
struct device *dev;
|
||||
void __iomem *dbi_base;
|
||||
void __iomem *dbi_base2;
|
||||
/* Used when iatu_unroll_enabled is true */
|
||||
void __iomem *atu_base;
|
||||
u32 num_viewport;
|
||||
u8 iatu_unroll_enabled;
|
||||
struct pcie_port pp;
|
||||
|
|
@ -289,6 +299,16 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
|
|||
return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
|
||||
}
|
||||
|
||||
static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)
|
||||
{
|
||||
__dw_pcie_write_dbi(pci, pci->atu_base, reg, 0x4, val);
|
||||
}
|
||||
|
||||
static inline u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg)
|
||||
{
|
||||
return __dw_pcie_read_dbi(pci, pci->atu_base, reg, 0x4);
|
||||
}
|
||||
|
||||
static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
|
||||
{
|
||||
u32 reg;
|
||||
|
|
|
|||
|
|
@ -202,7 +202,7 @@ static int histb_pcie_host_init(struct pcie_port *pp)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct dw_pcie_host_ops histb_pcie_host_ops = {
|
||||
static const struct dw_pcie_host_ops histb_pcie_host_ops = {
|
||||
.rd_own_conf = histb_pcie_rd_own_conf,
|
||||
.wr_own_conf = histb_pcie_wr_own_conf,
|
||||
.host_init = histb_pcie_host_init,
|
||||
|
|
|
|||
|
|
@ -440,6 +440,7 @@
|
|||
#define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1)
|
||||
|
||||
#define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30)
|
||||
#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16)
|
||||
#define IMX6SX_GPR12_PCIE_RX_EQ_MASK (0x7 << 0)
|
||||
#define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue