ARM: tegra: add clk_prepare/clk_unprepare
Use clk_prepare/clk_unprepare as required by the generic clk framework. Tested on Ventana and Cardhu. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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cfaf025112
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6a5278d071
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@ -189,8 +189,8 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
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return PTR_ERR(emc_clk);
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}
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clk_enable(emc_clk);
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clk_enable(cpu_clk);
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clk_prepare_enable(emc_clk);
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clk_prepare_enable(cpu_clk);
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cpufreq_frequency_table_cpuinfo(policy, freq_table);
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cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
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@ -212,7 +212,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
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static int tegra_cpu_exit(struct cpufreq_policy *policy)
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{
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cpufreq_frequency_table_cpuinfo(policy, freq_table);
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clk_disable(emc_clk);
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clk_disable_unprepare(emc_clk);
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clk_put(emc_clk);
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clk_put(cpu_clk);
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return 0;
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@ -720,7 +720,7 @@ int __init tegra_dma_init(void)
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ret = PTR_ERR(c);
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goto fail;
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}
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ret = clk_enable(c);
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ret = clk_prepare_enable(c);
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if (ret != 0) {
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pr_err("Unable to enable clock for APB DMA\n");
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goto fail;
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@ -723,9 +723,9 @@ static int tegra_pcie_power_regate(void)
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tegra_pcie_xclk_clamp(false);
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clk_enable(tegra_pcie.afi_clk);
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clk_enable(tegra_pcie.pex_clk);
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return clk_enable(tegra_pcie.pll_e);
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clk_prepare_enable(tegra_pcie.afi_clk);
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clk_prepare_enable(tegra_pcie.pex_clk);
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return clk_prepare_enable(tegra_pcie.pll_e);
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}
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static int tegra_pcie_clocks_get(void)
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@ -146,7 +146,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
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if (ret)
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goto err_power;
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ret = clk_enable(clk);
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ret = clk_prepare_enable(clk);
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if (ret)
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goto err_clk;
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@ -162,7 +162,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
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return 0;
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err_clamp:
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clk_disable(clk);
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clk_disable_unprepare(clk);
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err_clk:
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tegra_powergate_power_off(id);
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err_power:
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@ -189,7 +189,7 @@ static void __init tegra_init_timer(void)
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" Assuming 12Mhz input clock.\n");
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rate = 12000000;
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} else {
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clk_enable(clk);
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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}
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@ -201,7 +201,7 @@ static void __init tegra_init_timer(void)
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if (IS_ERR(clk))
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pr_warn("Unable to get rtc-tegra clock\n");
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else
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clk_enable(clk);
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clk_prepare_enable(clk);
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switch (rate) {
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case 12000000:
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@ -247,7 +247,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
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unsigned long val, flags;
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void __iomem *base = phy->pad_regs;
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clk_enable(phy->pad_clk);
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clk_prepare_enable(phy->pad_clk);
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spin_lock_irqsave(&utmip_pad_lock, flags);
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@ -259,7 +259,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
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spin_unlock_irqrestore(&utmip_pad_lock, flags);
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clk_disable(phy->pad_clk);
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clk_disable_unprepare(phy->pad_clk);
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}
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static int utmip_pad_power_off(struct tegra_usb_phy *phy)
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@ -272,7 +272,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
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return -EINVAL;
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}
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clk_enable(phy->pad_clk);
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clk_prepare_enable(phy->pad_clk);
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spin_lock_irqsave(&utmip_pad_lock, flags);
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@ -284,7 +284,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
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spin_unlock_irqrestore(&utmip_pad_lock, flags);
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clk_disable(phy->pad_clk);
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clk_disable_unprepare(phy->pad_clk);
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return 0;
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}
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@ -580,7 +580,7 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
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msleep(5);
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gpio_direction_output(config->reset_gpio, 1);
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clk_enable(phy->clk);
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clk_prepare_enable(phy->clk);
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msleep(1);
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val = readl(base + USB_SUSP_CTRL);
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@ -689,7 +689,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
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err = PTR_ERR(phy->pll_u);
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goto err0;
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}
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clk_enable(phy->pll_u);
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clk_prepare_enable(phy->pll_u);
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parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
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for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
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@ -735,7 +735,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
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return phy;
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err1:
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clk_disable(phy->pll_u);
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clk_disable_unprepare(phy->pll_u);
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clk_put(phy->pll_u);
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err0:
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kfree(phy);
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@ -810,7 +810,7 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
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clk_put(phy->clk);
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else
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utmip_pad_close(phy);
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clk_disable(phy->pll_u);
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clk_disable_unprepare(phy->pll_u);
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clk_put(phy->pll_u);
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kfree(phy);
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}
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