ARM: tegra: add clk_prepare/clk_unprepare

Use clk_prepare/clk_unprepare as required by the generic clk framework.

Tested on Ventana and Cardhu.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Prashant Gaikwad 2012-06-05 09:59:35 +05:30 committed by Stephen Warren
parent cfaf025112
commit 6a5278d071
6 changed files with 19 additions and 19 deletions

View File

@ -189,8 +189,8 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
return PTR_ERR(emc_clk); return PTR_ERR(emc_clk);
} }
clk_enable(emc_clk); clk_prepare_enable(emc_clk);
clk_enable(cpu_clk); clk_prepare_enable(cpu_clk);
cpufreq_frequency_table_cpuinfo(policy, freq_table); cpufreq_frequency_table_cpuinfo(policy, freq_table);
cpufreq_frequency_table_get_attr(freq_table, policy->cpu); cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
@ -212,7 +212,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
static int tegra_cpu_exit(struct cpufreq_policy *policy) static int tegra_cpu_exit(struct cpufreq_policy *policy)
{ {
cpufreq_frequency_table_cpuinfo(policy, freq_table); cpufreq_frequency_table_cpuinfo(policy, freq_table);
clk_disable(emc_clk); clk_disable_unprepare(emc_clk);
clk_put(emc_clk); clk_put(emc_clk);
clk_put(cpu_clk); clk_put(cpu_clk);
return 0; return 0;

View File

@ -720,7 +720,7 @@ int __init tegra_dma_init(void)
ret = PTR_ERR(c); ret = PTR_ERR(c);
goto fail; goto fail;
} }
ret = clk_enable(c); ret = clk_prepare_enable(c);
if (ret != 0) { if (ret != 0) {
pr_err("Unable to enable clock for APB DMA\n"); pr_err("Unable to enable clock for APB DMA\n");
goto fail; goto fail;

View File

@ -723,9 +723,9 @@ static int tegra_pcie_power_regate(void)
tegra_pcie_xclk_clamp(false); tegra_pcie_xclk_clamp(false);
clk_enable(tegra_pcie.afi_clk); clk_prepare_enable(tegra_pcie.afi_clk);
clk_enable(tegra_pcie.pex_clk); clk_prepare_enable(tegra_pcie.pex_clk);
return clk_enable(tegra_pcie.pll_e); return clk_prepare_enable(tegra_pcie.pll_e);
} }
static int tegra_pcie_clocks_get(void) static int tegra_pcie_clocks_get(void)

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@ -146,7 +146,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
if (ret) if (ret)
goto err_power; goto err_power;
ret = clk_enable(clk); ret = clk_prepare_enable(clk);
if (ret) if (ret)
goto err_clk; goto err_clk;
@ -162,7 +162,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
return 0; return 0;
err_clamp: err_clamp:
clk_disable(clk); clk_disable_unprepare(clk);
err_clk: err_clk:
tegra_powergate_power_off(id); tegra_powergate_power_off(id);
err_power: err_power:

View File

@ -189,7 +189,7 @@ static void __init tegra_init_timer(void)
" Assuming 12Mhz input clock.\n"); " Assuming 12Mhz input clock.\n");
rate = 12000000; rate = 12000000;
} else { } else {
clk_enable(clk); clk_prepare_enable(clk);
rate = clk_get_rate(clk); rate = clk_get_rate(clk);
} }
@ -201,7 +201,7 @@ static void __init tegra_init_timer(void)
if (IS_ERR(clk)) if (IS_ERR(clk))
pr_warn("Unable to get rtc-tegra clock\n"); pr_warn("Unable to get rtc-tegra clock\n");
else else
clk_enable(clk); clk_prepare_enable(clk);
switch (rate) { switch (rate) {
case 12000000: case 12000000:

View File

@ -247,7 +247,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
unsigned long val, flags; unsigned long val, flags;
void __iomem *base = phy->pad_regs; void __iomem *base = phy->pad_regs;
clk_enable(phy->pad_clk); clk_prepare_enable(phy->pad_clk);
spin_lock_irqsave(&utmip_pad_lock, flags); spin_lock_irqsave(&utmip_pad_lock, flags);
@ -259,7 +259,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
spin_unlock_irqrestore(&utmip_pad_lock, flags); spin_unlock_irqrestore(&utmip_pad_lock, flags);
clk_disable(phy->pad_clk); clk_disable_unprepare(phy->pad_clk);
} }
static int utmip_pad_power_off(struct tegra_usb_phy *phy) static int utmip_pad_power_off(struct tegra_usb_phy *phy)
@ -272,7 +272,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
return -EINVAL; return -EINVAL;
} }
clk_enable(phy->pad_clk); clk_prepare_enable(phy->pad_clk);
spin_lock_irqsave(&utmip_pad_lock, flags); spin_lock_irqsave(&utmip_pad_lock, flags);
@ -284,7 +284,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
spin_unlock_irqrestore(&utmip_pad_lock, flags); spin_unlock_irqrestore(&utmip_pad_lock, flags);
clk_disable(phy->pad_clk); clk_disable_unprepare(phy->pad_clk);
return 0; return 0;
} }
@ -580,7 +580,7 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
msleep(5); msleep(5);
gpio_direction_output(config->reset_gpio, 1); gpio_direction_output(config->reset_gpio, 1);
clk_enable(phy->clk); clk_prepare_enable(phy->clk);
msleep(1); msleep(1);
val = readl(base + USB_SUSP_CTRL); val = readl(base + USB_SUSP_CTRL);
@ -689,7 +689,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
err = PTR_ERR(phy->pll_u); err = PTR_ERR(phy->pll_u);
goto err0; goto err0;
} }
clk_enable(phy->pll_u); clk_prepare_enable(phy->pll_u);
parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
@ -735,7 +735,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
return phy; return phy;
err1: err1:
clk_disable(phy->pll_u); clk_disable_unprepare(phy->pll_u);
clk_put(phy->pll_u); clk_put(phy->pll_u);
err0: err0:
kfree(phy); kfree(phy);
@ -810,7 +810,7 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
clk_put(phy->clk); clk_put(phy->clk);
else else
utmip_pad_close(phy); utmip_pad_close(phy);
clk_disable(phy->pll_u); clk_disable_unprepare(phy->pll_u);
clk_put(phy->pll_u); clk_put(phy->pll_u);
kfree(phy); kfree(phy);
} }