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[Blackfin] arch: update reboot code to match latest info (really just copy from u-boot) 

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Mike Frysinger 2008-04-23 08:01:31 +08:00 committed by Bryan Wu
parent 9fcdc78c5e
commit 6a42a91019
1 changed files with 40 additions and 29 deletions
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69
arch/blackfin/kernel/reboot.c
View File

@ -11,45 +11,56 @@
#include <asm/reboot.h> #include <asm/reboot.h>
#include <asm/system.h> #include <asm/system.h>
#if defined(BF537_FAMILY) || defined(BF533_FAMILY) || defined(BF527_FAMILY) /* A system soft reset makes external memory unusable so force
#define SYSCR_VAL 0x0 * this function into L1. We use the compiler ssync here rather
#elif defined(BF561_FAMILY) * than SSYNC() because it's safe (no interrupts and such) and
#define SYSCR_VAL 0x20 * we save some L1. We do not need to force sanity in the SYSCR
#elif defined(BF548_FAMILY) * register as the BMODE selection bit is cleared by the soft
#define SYSCR_VAL 0x10 * reset while the Core B bit (on dual core parts) is cleared by
#endif * the core reset.
/*
* Delay min 5 SCLK cycles using worst case CCLK/SCLK ratio (15)
*/
#define SWRST_DELAY (5 * 15)
/* A system soft reset makes external memory unusable
* so force this function into L1.
*/ */
__attribute__((l1_text)) __attribute__((l1_text))
void bfin_reset(void) void bfin_reset(void)
{ {
/* force BMODE and disable Core B (as needed) */ /* Wait for completion of "system" events such as cache line
bfin_write_SYSCR(SYSCR_VAL); * line fills so that we avoid infinite stalls later on as
* much as possible. This code is in L1, so it won't trigger
/* we use asm ssync here because it's save and we save some L1 */ * any such event after this point in time.
asm("ssync;"); */
__builtin_bfin_ssync();
while (1) { while (1) {
/* initiate system soft reset with magic 0x7 */ /* Initiate System software reset. */
bfin_write_SWRST(0x7); bfin_write_SWRST(0x7);
/* Wait for System reset to actually reset, needs to be 5 SCLKs, */ /* Due to the way reset is handled in the hardware, we need
/* Assume CCLK / SCLK ratio is worst case (15), and use 5*15 */ * to delay for 7 SCLKS. The only reliable way to do this is
* to calculate the CCLK/SCLK ratio and multiply 7. For now,
* we'll assume worse case which is a 1:15 ratio.
*/
asm(
"LSETUP (1f, 1f) LC0 = %0\n"
"1: nop;"
:
: "a" (15 * 7)
: "LC0", "LB0", "LT0"
);
asm("LSETUP(.Lfoo,.Lfoo) LC0 = %0\n .Lfoo: NOP;\n" /* Clear System software reset */
: : "a" (SWRST_DELAY) : "LC0", "LT0", "LB0");
/* clear system soft reset */
bfin_write_SWRST(0); bfin_write_SWRST(0);
asm("ssync;");
/* issue core reset */ /* Wait for the SWRST write to complete. Cannot rely on SSYNC
* though as the System state is all reset now.
*/
asm(
"LSETUP (1f, 1f) LC1 = %0\n"
"1: nop;"
:
: "a" (15 * 1)
: "LC1", "LB1", "LT1"
);
/* Issue core reset */
asm("raise 1"); asm("raise 1");
} }
} }