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mmc: sdhci-esdhc-imx: fix mmc ddr mode regression issue 

It's caused by the platform driver was still using MMC_TIMING_UHS_DDR50
for MMC DDR mode which needs update too.

Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Reported-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
[Ulf Hansson] Resolved conflict
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
This commit is contained in:
Aisheng Dong 2014-05-09 14:53:15 +08:00 committed by Chris Ball
parent 706adf6bc3
commit 69f5bf38f9
1 changed files with 1 additions and 0 deletions
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1
drivers/mmc/host/sdhci-esdhc-imx.c
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@ -852,6 +852,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
case MMC_TIMING_MMC_HS200:
break;
case MMC_TIMING_UHS_DDR50:
case MMC_TIMING_MMC_DDR52:
writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
ESDHC_MIX_CTRL_DDREN,
host->ioaddr + ESDHC_MIX_CTRL);