USB: musb: enable low level DMA operation for Blackfin
- DMA registers in Blackfin have different layout - DMA interrupt flags need to be cleared by software Signed-off-by: Bryan Wu <cooloney@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Bryan Wu
Greg Kroah-Hartman
parent
2c557a4a98
commit
6995eb68aa
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@ -34,58 +34,7 @@
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include "musb_core.h"
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#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
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#include "omap2430.h"
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#endif
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#define MUSB_HSDMA_BASE 0x200
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#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
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#define MUSB_HSDMA_CONTROL 0x4
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#define MUSB_HSDMA_ADDRESS 0x8
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#define MUSB_HSDMA_COUNT 0xc
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#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
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(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
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/* control register (16-bit): */
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#define MUSB_HSDMA_ENABLE_SHIFT 0
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#define MUSB_HSDMA_TRANSMIT_SHIFT 1
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#define MUSB_HSDMA_MODE1_SHIFT 2
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#define MUSB_HSDMA_IRQENABLE_SHIFT 3
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#define MUSB_HSDMA_ENDPOINT_SHIFT 4
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#define MUSB_HSDMA_BUSERROR_SHIFT 8
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#define MUSB_HSDMA_BURSTMODE_SHIFT 9
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#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
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#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
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#define MUSB_HSDMA_BURSTMODE_INCR4 1
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#define MUSB_HSDMA_BURSTMODE_INCR8 2
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#define MUSB_HSDMA_BURSTMODE_INCR16 3
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#define MUSB_HSDMA_CHANNELS 8
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struct musb_dma_controller;
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struct musb_dma_channel {
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struct dma_channel channel;
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struct musb_dma_controller *controller;
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u32 start_addr;
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u32 len;
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u16 max_packet_sz;
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u8 idx;
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u8 epnum;
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u8 transmit;
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};
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struct musb_dma_controller {
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struct dma_controller controller;
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struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
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void *private_data;
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void __iomem *base;
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u8 channel_count;
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u8 used_channels;
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u8 irq;
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};
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#include "musbhsdma.h"
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static int dma_controller_start(struct dma_controller *c)
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{
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@ -203,12 +152,8 @@ static void configure_channel(struct dma_channel *channel,
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: 0);
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/* address/count */
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musb_writel(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
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dma_addr);
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musb_writel(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
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len);
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musb_write_hsdma_addr(mbase, bchannel, dma_addr);
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musb_write_hsdma_count(mbase, bchannel, len);
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/* control (this should start things) */
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musb_writew(mbase,
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@ -279,13 +224,8 @@ static int dma_channel_abort(struct dma_channel *channel)
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
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0);
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musb_writel(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
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0);
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musb_writel(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
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0);
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musb_write_hsdma_addr(mbase, bchannel, 0);
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musb_write_hsdma_count(mbase, bchannel, 0);
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channel->status = MUSB_DMA_STATUS_FREE;
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}
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@ -333,10 +273,8 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
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} else {
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u8 devctl;
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addr = musb_readl(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(
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bchannel,
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MUSB_HSDMA_ADDRESS));
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addr = musb_read_hsdma_addr(mbase,
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bchannel);
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channel->actual_len = addr
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- musb_channel->start_addr;
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@ -375,6 +313,12 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
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}
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}
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}
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#ifdef CONFIG_BLACKFIN
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/* Clear DMA interrup flags */
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musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
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#endif
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retval = IRQ_HANDLED;
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done:
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spin_unlock_irqrestore(&musb->lock, flags);
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@ -0,0 +1,149 @@
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/*
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* MUSB OTG driver - support for Mentor's DMA controller
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*
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* Copyright 2005 Mentor Graphics Corporation
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* Copyright (C) 2005-2007 by Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
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#include "omap2430.h"
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#endif
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#ifndef CONFIG_BLACKFIN
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#define MUSB_HSDMA_BASE 0x200
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#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
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#define MUSB_HSDMA_CONTROL 0x4
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#define MUSB_HSDMA_ADDRESS 0x8
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#define MUSB_HSDMA_COUNT 0xc
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#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
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(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
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#define musb_read_hsdma_addr(mbase, bchannel) \
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musb_readl(mbase, \
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
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#define musb_write_hsdma_addr(mbase, bchannel, addr) \
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musb_writel(mbase, \
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
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addr)
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#define musb_write_hsdma_count(mbase, bchannel, len) \
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musb_writel(mbase, \
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
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len)
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#else
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#define MUSB_HSDMA_BASE 0x400
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#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
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#define MUSB_HSDMA_CONTROL 0x04
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#define MUSB_HSDMA_ADDR_LOW 0x08
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#define MUSB_HSDMA_ADDR_HIGH 0x0C
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#define MUSB_HSDMA_COUNT_LOW 0x10
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#define MUSB_HSDMA_COUNT_HIGH 0x14
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#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
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(MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
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static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
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{
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u32 addr = musb_readw(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
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addr = addr << 16;
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addr |= musb_readw(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
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return addr;
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}
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static inline void musb_write_hsdma_addr(void __iomem *mbase,
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u8 bchannel, dma_addr_t dma_addr)
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{
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
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((u16)((u32) dma_addr & 0xFFFF)));
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
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((u16)(((u32) dma_addr >> 16) & 0xFFFF)));
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}
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static inline void musb_write_hsdma_count(void __iomem *mbase,
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u8 bchannel, u32 len)
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{
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),
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((u16)((u32) len & 0xFFFF)));
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
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((u16)(((u32) len >> 16) & 0xFFFF)));
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}
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#endif /* CONFIG_BLACKFIN */
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/* control register (16-bit): */
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#define MUSB_HSDMA_ENABLE_SHIFT 0
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#define MUSB_HSDMA_TRANSMIT_SHIFT 1
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#define MUSB_HSDMA_MODE1_SHIFT 2
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#define MUSB_HSDMA_IRQENABLE_SHIFT 3
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#define MUSB_HSDMA_ENDPOINT_SHIFT 4
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#define MUSB_HSDMA_BUSERROR_SHIFT 8
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#define MUSB_HSDMA_BURSTMODE_SHIFT 9
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#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
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#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
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#define MUSB_HSDMA_BURSTMODE_INCR4 1
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#define MUSB_HSDMA_BURSTMODE_INCR8 2
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#define MUSB_HSDMA_BURSTMODE_INCR16 3
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#define MUSB_HSDMA_CHANNELS 8
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struct musb_dma_controller;
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struct musb_dma_channel {
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struct dma_channel channel;
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struct musb_dma_controller *controller;
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u32 start_addr;
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u32 len;
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u16 max_packet_sz;
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u8 idx;
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u8 epnum;
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u8 transmit;
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};
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struct musb_dma_controller {
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struct dma_controller controller;
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struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
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void *private_data;
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void __iomem *base;
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u8 channel_count;
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u8 used_channels;
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u8 irq;
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};
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