powerpc: Remove CONFIG_POWER4_ONLY
Remove CONFIG_POWER4_ONLY, the option is badly named and only does two things: - It wraps the MMU segment table code. With feature fixups there is little downside to compiling this in. - It uses the newer mtocrf instruction in various assembly functions. Instead of making this a compile option just do it at runtime via a feature fixup. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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694caf0255
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@ -1,5 +1,4 @@
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CONFIG_PPC64=y
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CONFIG_PPC64=y
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CONFIG_POWER4_ONLY=y
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CONFIG_ALTIVEC=y
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CONFIG_ALTIVEC=y
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CONFIG_SMP=y
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CONFIG_SMP=y
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CONFIG_NR_CPUS=4
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CONFIG_NR_CPUS=4
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@ -1,5 +1,4 @@
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CONFIG_PPC64=y
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CONFIG_PPC64=y
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CONFIG_POWER4_ONLY=y
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CONFIG_SMP=y
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CONFIG_SMP=y
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CONFIG_NR_CPUS=4
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CONFIG_NR_CPUS=4
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CONFIG_EXPERIMENTAL=y
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CONFIG_EXPERIMENTAL=y
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@ -1,5 +1,4 @@
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CONFIG_PPC64=y
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CONFIG_PPC64=y
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CONFIG_POWER4_ONLY=y
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CONFIG_ALTIVEC=y
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CONFIG_ALTIVEC=y
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# CONFIG_VIRT_CPU_ACCOUNTING is not set
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# CONFIG_VIRT_CPU_ACCOUNTING is not set
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CONFIG_SMP=y
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CONFIG_SMP=y
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@ -29,18 +29,9 @@
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#define PPC_LLARX(t, a, b, eh) PPC_LDARX(t, a, b, eh)
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#define PPC_LLARX(t, a, b, eh) PPC_LDARX(t, a, b, eh)
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#define PPC_STLCX stringify_in_c(stdcx.)
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#define PPC_STLCX stringify_in_c(stdcx.)
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#define PPC_CNTLZL stringify_in_c(cntlzd)
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#define PPC_CNTLZL stringify_in_c(cntlzd)
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#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), (RS))
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#define PPC_LR_STKOFF 16
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#define PPC_LR_STKOFF 16
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#define PPC_MIN_STKFRM 112
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#define PPC_MIN_STKFRM 112
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/* Move to CR, single-entry optimized version. Only available
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* on POWER4 and later.
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*/
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#ifdef CONFIG_POWER4_ONLY
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#define PPC_MTOCRF stringify_in_c(mtocrf)
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#else
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#define PPC_MTOCRF stringify_in_c(mtcrf)
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#endif
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#else /* 32-bit */
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#else /* 32-bit */
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/* operations for longs and pointers */
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/* operations for longs and pointers */
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@ -369,7 +369,15 @@ BEGIN_FTR_SECTION \
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END_FTR_SECTION_IFCLR(CPU_FTR_601)
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END_FTR_SECTION_IFCLR(CPU_FTR_601)
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#endif
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#endif
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#ifdef CONFIG_PPC64
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#define MTOCRF(FXM, RS) \
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BEGIN_FTR_SECTION_NESTED(848); \
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mtcrf (FXM), (RS); \
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FTR_SECTION_ELSE_NESTED(848); \
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mtocrf (FXM), (RS); \
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ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
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#endif
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/*
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/*
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* This instruction is not implemented on the PPC 603 or 601; however, on
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* This instruction is not implemented on the PPC 603 or 601; however, on
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* the 403GCX and 405GP tlbia IS defined and tlbie is not.
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* the 403GCX and 405GP tlbia IS defined and tlbie is not.
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@ -94,12 +94,10 @@ machine_check_pSeries_1:
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data_access_pSeries:
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data_access_pSeries:
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HMT_MEDIUM
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HMT_MEDIUM
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SET_SCRATCH0(r13)
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SET_SCRATCH0(r13)
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#ifndef CONFIG_POWER4_ONLY
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BEGIN_FTR_SECTION
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BEGIN_FTR_SECTION
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b data_access_check_stab
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b data_access_check_stab
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data_access_not_stab:
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data_access_not_stab:
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
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#endif
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EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD,
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EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD,
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KVMTEST, 0x300)
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KVMTEST, 0x300)
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@ -301,7 +299,6 @@ machine_check_fwnmi:
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EXC_STD, KVMTEST, 0x200)
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EXC_STD, KVMTEST, 0x200)
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KVM_HANDLER_SKIP(PACA_EXMC, EXC_STD, 0x200)
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KVM_HANDLER_SKIP(PACA_EXMC, EXC_STD, 0x200)
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#ifndef CONFIG_POWER4_ONLY
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/* moved from 0x300 */
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/* moved from 0x300 */
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data_access_check_stab:
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data_access_check_stab:
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GET_PACA(r13)
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GET_PACA(r13)
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@ -328,7 +325,6 @@ do_stab_bolted_pSeries:
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GET_SCRATCH0(r10)
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GET_SCRATCH0(r10)
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std r10,PACA_EXSLB+EX_R13(r13)
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std r10,PACA_EXSLB+EX_R13(r13)
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EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD)
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EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD)
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#endif /* CONFIG_POWER4_ONLY */
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KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x300)
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KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x300)
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KVM_HANDLER_SKIP(PACA_EXSLB, EXC_STD, 0x380)
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KVM_HANDLER_SKIP(PACA_EXSLB, EXC_STD, 0x380)
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@ -30,7 +30,7 @@ _GLOBAL(__copy_tofrom_user_base)
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dcbt 0,r4
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dcbt 0,r4
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beq .Lcopy_page_4K
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beq .Lcopy_page_4K
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andi. r6,r6,7
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andi. r6,r6,7
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PPC_MTOCRF 0x01,r5
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PPC_MTOCRF(0x01,r5)
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blt cr1,.Lshort_copy
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blt cr1,.Lshort_copy
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/* Below we want to nop out the bne if we're on a CPU that has the
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/* Below we want to nop out the bne if we're on a CPU that has the
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* CPU_FTR_UNALIGNED_LD_STD bit set and the CPU_FTR_CP_USE_DCBTZ bit
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* CPU_FTR_UNALIGNED_LD_STD bit set and the CPU_FTR_CP_USE_DCBTZ bit
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@ -186,7 +186,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
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blr
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blr
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.Ldst_unaligned:
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.Ldst_unaligned:
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PPC_MTOCRF 0x01,r6 /* put #bytes to 8B bdry into cr7 */
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PPC_MTOCRF(0x01,r6) /* put #bytes to 8B bdry into cr7 */
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subf r5,r6,r5
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subf r5,r6,r5
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li r7,0
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li r7,0
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cmpldi cr1,r5,16
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cmpldi cr1,r5,16
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@ -201,7 +201,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
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2: bf cr7*4+1,3f
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2: bf cr7*4+1,3f
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37: lwzx r0,r7,r4
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37: lwzx r0,r7,r4
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83: stwx r0,r7,r3
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83: stwx r0,r7,r3
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3: PPC_MTOCRF 0x01,r5
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3: PPC_MTOCRF(0x01,r5)
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add r4,r6,r4
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add r4,r6,r4
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add r3,r6,r3
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add r3,r6,r3
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b .Ldst_aligned
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b .Ldst_aligned
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@ -19,7 +19,7 @@ _GLOBAL(memset)
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rlwimi r4,r4,16,0,15
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rlwimi r4,r4,16,0,15
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cmplw cr1,r5,r0 /* do we get that far? */
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cmplw cr1,r5,r0 /* do we get that far? */
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rldimi r4,r4,32,0
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rldimi r4,r4,32,0
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PPC_MTOCRF 1,r0
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PPC_MTOCRF(1,r0)
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mr r6,r3
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mr r6,r3
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blt cr1,8f
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blt cr1,8f
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beq+ 3f /* if already 8-byte aligned */
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beq+ 3f /* if already 8-byte aligned */
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@ -49,7 +49,7 @@ _GLOBAL(memset)
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bdnz 4b
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bdnz 4b
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5: srwi. r0,r5,3
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5: srwi. r0,r5,3
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clrlwi r5,r5,29
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clrlwi r5,r5,29
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PPC_MTOCRF 1,r0
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PPC_MTOCRF(1,r0)
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beq 8f
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beq 8f
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bf 29,6f
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bf 29,6f
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std r4,0(r6)
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std r4,0(r6)
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std r4,0(r6)
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std r4,0(r6)
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addi r6,r6,8
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addi r6,r6,8
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8: cmpwi r5,0
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8: cmpwi r5,0
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PPC_MTOCRF 1,r5
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PPC_MTOCRF(1,r5)
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beqlr+
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beqlr+
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bf 29,9f
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bf 29,9f
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stw r4,0(r6)
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stw r4,0(r6)
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@ -12,7 +12,7 @@
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.align 7
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.align 7
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_GLOBAL(memcpy)
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_GLOBAL(memcpy)
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std r3,48(r1) /* save destination pointer for return value */
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std r3,48(r1) /* save destination pointer for return value */
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PPC_MTOCRF 0x01,r5
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PPC_MTOCRF(0x01,r5)
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cmpldi cr1,r5,16
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cmpldi cr1,r5,16
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neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry
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neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry
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andi. r6,r6,7
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andi. r6,r6,7
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@ -154,7 +154,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
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blr
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blr
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.Ldst_unaligned:
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.Ldst_unaligned:
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PPC_MTOCRF 0x01,r6 # put #bytes to 8B bdry into cr7
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PPC_MTOCRF(0x01,r6) # put #bytes to 8B bdry into cr7
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subf r5,r6,r5
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subf r5,r6,r5
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li r7,0
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li r7,0
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cmpldi cr1,r5,16
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cmpldi cr1,r5,16
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@ -169,7 +169,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
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2: bf cr7*4+1,3f
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2: bf cr7*4+1,3f
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lwzx r0,r7,r4
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lwzx r0,r7,r4
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stwx r0,r7,r3
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stwx r0,r7,r3
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3: PPC_MTOCRF 0x01,r5
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3: PPC_MTOCRF(0x01,r5)
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add r4,r6,r4
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add r4,r6,r4
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add r3,r6,r3
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add r3,r6,r3
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b .Ldst_aligned
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b .Ldst_aligned
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@ -86,15 +86,6 @@ config PPC_BOOK3E
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def_bool y
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def_bool y
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depends on PPC_BOOK3E_64
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depends on PPC_BOOK3E_64
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config POWER4_ONLY
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bool "Optimize for POWER4"
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depends on PPC64 && PPC_BOOK3S
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default n
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---help---
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Cause the compiler to optimize for POWER4/POWER5/PPC970 processors.
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The resulting binary will not work on POWER3 or RS64 processors
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when compiled with binutils 2.15 or later.
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config 6xx
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config 6xx
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def_bool y
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def_bool y
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depends on PPC32 && PPC_BOOK3S
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depends on PPC32 && PPC_BOOK3S
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