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ARM: SoC changes for v5.8 

One new platform gets added, the Realtek RTD1195, which is an older
 Cortex-a7 based relative of the RTD12xx chips that are already supported
 in arch/arm64. The platform may also be extended to support running
 32-bit kernels on those 64-bit chips for memory-constrained machines.
 
 In the Renesas shmobile platform, we gain support for "RZ/G1H" or R8A7742,
 an eight-core chip based on Cortex-A15 and Cortex-A7 cores, originally
 released in 2016 as one of the last high-end 32-bit designs.
 
 There is ongoing cleanup for the integrator, tegra, imx, and omap2
 platforms, with integrator getting very close to the goal of having
 zero code in arch/arm/, and omap2 moving more of the chip specifics
 from old board code into device tree files.
 
 The Versatile Express platform is made more modular, with built-in
 drivers now becoming loadable modules. This is part of a greater effort
 for the Android OS to have a common kernel binary for all platforms and
 any platform specific code in loadable modules.
 
 The PXA platform drops support for Compulab's pxa2xx boards that had
 rather unusual flash and PCI drivers but no known users remaining.
 All device drivers specific to those boards can now get removed as
 well.
 
 Across platforms, there is ongoing cleanup, with Geert and Rob
 revisiting some a lot of Kconfig options.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-soc-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC updates from Arnd Bergmann:
 "One new platform gets added, the Realtek RTD1195, which is an older
  Cortex-a7 based relative of the RTD12xx chips that are already
  supported in arch/arm64. The platform may also be extended to support
  running 32-bit kernels on those 64-bit chips for memory-constrained
  machines.

  In the Renesas shmobile platform, we gain support for "RZ/G1H" or
  R8A7742, an eight-core chip based on Cortex-A15 and Cortex-A7 cores,
  originally released in 2016 as one of the last high-end 32-bit
  designs.

  There is ongoing cleanup for the integrator, tegra, imx, and omap2
  platforms, with integrator getting very close to the goal of having
  zero code in arch/arm/, and omap2 moving more of the chip specifics
  from old board code into device tree files.

  The Versatile Express platform is made more modular, with built-in
  drivers now becoming loadable modules. This is part of a greater
  effort for the Android OS to have a common kernel binary for all
  platforms and any platform specific code in loadable modules.

  The PXA platform drops support for Compulab's pxa2xx boards that had
  rather unusual flash and PCI drivers but no known users remaining. All
  device drivers specific to those boards can now get removed as well.

  Across platforms, there is ongoing cleanup, with Geert and Rob
  revisiting some a lot of Kconfig options"

* tag 'arm-soc-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (94 commits)
  ARM: omap2: fix omap5_realtime_timer_init definition
  ARM: zynq: Don't select CONFIG_ICST
  ARM: OMAP2+: Fix regression for using local timer on non-SMP SoCs
  clk: versatile: Fix kconfig dependency on COMMON_CLK_VERSATILE
  ARM: davinci: fix build failure without I2C
  power: reset: vexpress: fix build issue
  power: vexpress: cleanup: use builtin_platform_driver
  power: vexpress: add suppress_bind_attrs to true
  Revert "ARM: vexpress: Don't select VEXPRESS_CONFIG"
  MAINTAINERS: pxa: remove Compulab arm/pxa support
  ARM: pxa: remove Compulab pxa2xx boards
  bus: arm-integrator-lm: Fix return value check in integrator_ap_lm_probe()
  soc: imx: move cpu code to drivers/soc/imx
  ARM: imx: move cpu definitions into a header
  ARM: imx: use device_initcall for imx_soc_device_init
  ARM: imx: pcm037: make pcm970_sja1000_platform_data static
  bus: ti-sysc: Timers no longer need legacy quirk handling
  ARM: OMAP2+: Drop old timer code for dmtimer and 32k counter
  ARM: dts: Configure system timers for omap2
  ARM: dts: Configure system timers for ti81xx
  ...
This commit is contained in:
Linus Torvalds 2020-06-04 19:47:11 -07:00
parent 587f17018a d2353bad2c
commit 694b5a5d31
145 changed files with 1635 additions and 6247 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

83
Documentation/devicetree/bindings/bus/arm,integrator-ap-lm.yaml Normal file
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@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/arm,integrator-ap-lm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Integrator/AP Logic Module extension bus
maintainers:
- Linus Walleij <linusw@kernel.org>
description: The Integrator/AP is a prototyping platform and as such has a
site for stacking up to four logic modules (LM) designed specifically for
use with this platform. A special system controller register can be read to
determine if a logic module is connected at index 0, 1, 2 or 3. The logic
module connector is described in this binding. The logic modules per se
then have their own specific per-module bindings and they will be described
as subnodes under this logic module extension bus.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 1
compatible:
items:
- const: arm,integrator-ap-lm
ranges: true
dma-ranges: true
patternProperties:
"^bus(@[0-9a-f]*)?$":
description: Nodes on the Logic Module bus represent logic modules
and are named with bus. The first module is at 0xc0000000, the second
at 0xd0000000 and so on until the top of the memory of the system at
0xffffffff. All information about the memory used by the module is
in ranges and dma-ranges.
type: object
required:
- compatible
required:
- compatible
examples:
- |
bus@c0000000 {
compatible = "arm,integrator-ap-lm";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xc0000000 0xc0000000 0x40000000>;
dma-ranges;
bus@c0000000 {
compatible = "simple-bus";
ranges = <0x00000000 0xc0000000 0x10000000>;
/* The Logic Modules sees the Core Module 0 RAM @80000000 */
dma-ranges = <0x00000000 0x80000000 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
serial@100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00100000 0x1000>;
interrupts-extended = <&impd1_vic 1>;
};
impd1_vic: interrupt-controller@3000000 {
compatible = "arm,pl192-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x03000000 0x1000>;
valid-mask = <0x00000bff>;
interrupts-extended = <&pic 9>;
};
};
};
additionalProperties: false

13
MAINTAINERS
View File

@ -1350,10 +1350,11 @@ F: arch/arm/mach-integrator/
F: arch/arm/mach-realview/
F: arch/arm/mach-versatile/
F: arch/arm/plat-versatile/
F: drivers/bus/arm-integrator-lm.c
F: drivers/clk/versatile/
F: drivers/i2c/busses/i2c-versatile.c
F: drivers/irqchip/irq-versatile-fpga.c
F: drivers/mtd/maps/physmap_of_versatile.c
F: drivers/mtd/maps/physmap-versatile.*
F: drivers/power/reset/arm-versatile-reboot.c
F: drivers/soc/versatile/
@ -1703,11 +1704,6 @@ S: Maintained
T: git git://git.armlinux.org.uk/~rmk/linux-arm.git clkdev
F: drivers/clk/clkdev.c
ARM/COMPULAB CM-X270/EM-X270 and CM-X300 MACHINE SUPPORT
M: Mike Rapoport <mike@compulab.co.il>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/CONEXANT DIGICOLOR MACHINE SUPPORT
M: Baruch Siach <baruch@tkos.co.il>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -2016,6 +2012,7 @@ F: arch/arm/mach-dove/
F: arch/arm/mach-mv78xx0/
F: arch/arm/mach-orion5x/
F: arch/arm/plat-orion/
F: drivers/soc/dove/
ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SOC support
M: Jason Cooper <jason@lakedaemon.net>
@ -2292,6 +2289,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-realtek-soc@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/realtek.yaml
F: arch/arm/boot/dts/rtd*
F: arch/arm/mach-realtek/
F: arch/arm64/boot/dts/realtek/
ARM/RENESAS ARM64 ARCHITECTURE
@ -3340,7 +3339,7 @@ L: bcm-kernel-feedback-list@broadcom.com
L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://github.com/anholt/linux
T: git git://git.kernel.org/pub/scm/linux/kernel/git/nsaenz/linux-rpi.git
F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
F: drivers/pci/controller/pcie-brcmstb.c
F: drivers/staging/vc04_services

4
arch/arm/Kconfig
View File

@ -702,6 +702,8 @@ source "arch/arm/mach-qcom/Kconfig"
source "arch/arm/mach-rda/Kconfig"
source "arch/arm/mach-realtek/Kconfig"
source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
@ -739,7 +741,6 @@ source "arch/arm/mach-ux500/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/plat-versatile/Kconfig"
source "arch/arm/mach-vt8500/Kconfig"
@ -1249,7 +1250,6 @@ config HAVE_ARM_ARCH_TIMER
bool "Architected timer support"
depends on CPU_V7
select ARM_ARCH_TIMER
select GENERIC_CLOCKEVENTS
help
This option enables support for the ARM architected timer

10
arch/arm/Kconfig.debug
View File

@ -976,6 +976,13 @@ choice
Say Y here if you want kernel low-level debugging support
via SCIF4 on Renesas RZ/G1E (R8A7745).
config DEBUG_RCAR_GEN2_SCIFA2
bool "Kernel low-level debugging messages via SCIFA2 on R8A7742"
depends on ARCH_R8A7742
help
Say Y here if you want kernel low-level debugging support
via SCIFA2 on Renesas RZ/G1H (R8A7742).
config DEBUG_RMOBILE_SCIFA0
bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
depends on ARCH_R8A73A4
@ -1577,6 +1584,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF1
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIFA2
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
@ -1696,6 +1704,7 @@ config DEBUG_UART_PHYS
default 0xe4007000 if DEBUG_HIP04_UART
default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0
default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1
default 0xe6c60000 if DEBUG_RCAR_GEN2_SCIFA2
default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4
default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2
default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
@ -1737,6 +1746,7 @@ config DEBUG_UART_PHYS
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \
DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
DEBUG_RCAR_GEN2_SCIFA2 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \

3
arch/arm/Makefile
View File

@ -148,6 +148,8 @@ head-y := arch/arm/kernel/head$(MMUEXT).o
textofs-y := 0x00008000
# We don't want the htc bootloader to corrupt kernel during resume
textofs-$(CONFIG_PM_H1940) := 0x00108000
# RTD1195 has Boot ROM at start of address space
textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000
# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
ifeq ($(CONFIG_ARCH_SA1100),y)
textofs-$(CONFIG_SA1111) := 0x00208000
@ -208,6 +210,7 @@ machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
machine-$(CONFIG_ARCH_PXA) += pxa
machine-$(CONFIG_ARCH_QCOM) += qcom
machine-$(CONFIG_ARCH_RDA) += rda
machine-$(CONFIG_ARCH_REALTEK) += realtek
machine-$(CONFIG_ARCH_REALVIEW) += realview
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_RPC) += rpc

6
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -330,9 +330,8 @@
};
};
target-module@31000 { /* 0x44e31000, ap 25 40.0 */
timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
ti,hwmods = "timer1";
reg = <0x31000 0x4>,
<0x31010 0x4>,
<0x31014 0x4>;
@ -1117,9 +1116,8 @@
};
};
target-module@40000 { /* 0x48040000, ap 22 1e.0 */
timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer2";
reg = <0x40000 0x4>,
<0x40010 0x4>,
<0x40014 0x4>;

20
arch/arm/boot/dts/am33xx.dtsi
View File

@ -619,3 +619,23 @@
#reset-cells = <1>;
};
};
/* Preferred always-on timer for clocksource */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer1_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer2_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};

24
arch/arm/boot/dts/am3517.dtsi
View File

@ -169,5 +169,25 @@
status = "disabled";
};
/include/ "am35xx-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
#include "am35xx-clocks.dtsi"
#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
/* Preferred always-on timer for clocksource */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt1_fck>;
assigned-clock-parents = <&sys_ck>;
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt2_fck>;
assigned-clock-parents = <&sys_ck>;
};
};

20
arch/arm/boot/dts/am4372.dtsi
View File

@ -553,3 +553,23 @@
#reset-cells = <1>;
};
};
/* Preferred always-on timer for clocksource */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer1_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer2_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};

7
arch/arm/boot/dts/am437x-l4.dtsi
View File

@ -328,9 +328,8 @@
};
};
target-module@31000 { /* 0x44e31000, ap 24 40.0 */
timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
ti,hwmods = "timer1";
reg = <0x31000 0x4>,
<0x31010 0x4>,
<0x31014 0x4>;
@ -450,7 +449,6 @@
target-module@86000 { /* 0x44e86000, ap 40 70.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "counter_32k";
reg = <0x86000 0x4>,
<0x86004 0x4>;
reg-names = "rev", "sysc";
@ -868,9 +866,8 @@
};
};
target-module@40000 { /* 0x48040000, ap 18 1e.0 */
timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer2";
reg = <0x40000 0x4>,
<0x40010 0x4>,
<0x40014 0x4>;

74
arch/arm/boot/dts/dm814x.dtsi
View File

@ -308,14 +308,30 @@
ti,hwmods = "mcspi4";
};
timer1: timer@2e000 {
compatible = "ti,dm814-timer";
reg = <0x2e000 0x2000>;
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
timer1_target: target-module@2e000 {
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&timer1_fck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2e000 0x1000>;
timer1: timer@0 {
compatible = "ti,am335x-timer-1ms";
reg = <0x0 0x400>;
interrupts = <67>;
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
};
uart1: uart@20000 {
@ -348,13 +364,29 @@
dma-names = "tx", "rx";
};
timer2: timer@40000 {
compatible = "ti,dm814-timer";
reg = <0x40000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
timer2_target: target-module@40000 {
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x40000 0x4>,
<0x40010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&timer2_fck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x40000 0x1000>;
timer2: timer@0 {
compatible = "ti,dm814-timer";
reg = <0 0x1000>;
interrupts = <68>;
clocks = <&timer2_fck>;
clock-names = "fck";
};
};
timer3: timer@42000 {
@ -735,3 +767,23 @@
};
#include "dm814x-clocks.dtsi"
/* Preferred always-on timer for clocksource */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer1_fck>;
assigned-clock-parents = <&devosc_ck>;
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer2_fck>;
assigned-clock-parents = <&devosc_ck>;
};
};

78
arch/arm/boot/dts/dm816x.dtsi
View File

@ -440,23 +440,55 @@
dma-names = "tx", "rx";
};
timer1: timer@4802e000 {
compatible = "ti,dm816-timer";
reg = <0x4802e000 0x2000>;
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
timer1_target: target-module@4802e000 {
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x4802e000 0x4>,
<0x4802e010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4802e000 0x1000>;
timer1: timer@0 {
compatible = "ti,dm816-timer";
reg = <0 0x1000>;
interrupts = <67>;
ti,timer-alwon;
clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
clock-names = "fck";
};
};
timer2: timer@48040000 {
compatible = "ti,dm816-timer";
reg = <0x48040000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
timer2_target: target-module@48040000 {
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x48040000 0x4>,
<0x48040010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x48040000 0x1000>;
timer2: timer@0 {
compatible = "ti,dm816-timer";
reg = <0 0x1000>;
interrupts = <68>;
clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
clock-names = "fck";
};
};
timer3: timer@48042000 {
@ -642,3 +674,23 @@
};
#include "dm816x-clocks.dtsi"
/* Preferred always-on timer for clocksource */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer1_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer2_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};

7
arch/arm/boot/dts/dra7-l4.dtsi
View File

@ -1143,7 +1143,6 @@
target-module@32000 { /* 0x48032000, ap 5 3e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer2";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
@ -1171,7 +1170,6 @@
target-module@34000 { /* 0x48034000, ap 7 46.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x34000 0x4>,
<0x34010 0x4>;
reg-names = "rev", "sysc";
@ -1199,7 +1197,6 @@
target-module@36000 { /* 0x48036000, ap 9 4e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x36000 0x4>,
<0x36010 0x4>;
reg-names = "rev", "sysc";
@ -4295,7 +4292,6 @@
target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4010 0x4>;
reg-names = "rev", "sysc";
@ -4430,9 +4426,8 @@
};
};
target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>;
reg-names = "rev", "sysc";

10
arch/arm/boot/dts/dra7.dtsi
View File

@ -1044,3 +1044,13 @@
reg = <0x1c00 0x60>;
};
};
/* Preferred always-on timer for clockevent */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
assigned-clock-parents = <&sys_32k_ck>;
};
};

31
arch/arm/boot/dts/omap2.dtsi
View File

@ -201,11 +201,32 @@
clock-frequency = <48000000>;
};
timer2: timer@4802a000 {
compatible = "ti,omap2420-timer";
reg = <0x4802a000 0x400>;
interrupts = <38>;
ti,hwmods = "timer2";
timer2_target: target-module@4802a000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x4802a000 0x4>,
<0x4802a010 0x4>,
<0x4802a014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt2_fck>, <&gpt2_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4802a000 0x1000>;
timer2: timer@0 {
compatible = "ti,omap2420-timer";
reg = <0 0x400>;
interrupts = <38>;
};
};
timer3: timer@48078000 {

68
arch/arm/boot/dts/omap2420.dtsi
View File

@ -68,10 +68,23 @@
};
};
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x20>;
ti,hwmods = "counter_32k";
target-module@4000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
clocks = <&func_32k_ck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4000 0x1000>;
counter32k: counter@0 {
compatible = "ti,omap-counter32k";
reg = <0 0x20>;
};
};
};
@ -194,12 +207,33 @@
};
};
timer1: timer@48028000 {
compatible = "ti,omap2420-timer";
reg = <0x48028000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";
ti,timer-alwon;
timer1_target: target-module@48028000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x48028000 0x4>,
<0x48028010 0x4>,
<0x48028014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt1_fck>, <&gpt1_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x48028000 0x1000>;
timer1: timer@0 {
compatible = "ti,omap2420-timer";
reg = <0 0x400>;
interrupts = <37>;
ti,timer-alwon;
};
};
wd_timer2: wdt@48022000 {
@ -218,5 +252,15 @@
compatible = "ti,omap2420-i2c";
};
/include/ "omap24xx-clocks.dtsi"
/include/ "omap2420-clocks.dtsi"
#include "omap24xx-clocks.dtsi"
#include "omap2420-clocks.dtsi"
/* Preferred always-on timer for clockevent */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt1_fck>;
assigned-clock-parents = <&func_32k_ck>;
};
};

68
arch/arm/boot/dts/omap2430.dtsi
View File

@ -81,10 +81,23 @@
};
};
counter32k: counter@20000 {
compatible = "ti,omap-counter32k";
reg = <0x20000 0x20>;
ti,hwmods = "counter_32k";
target-module@20000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x20000 0x4>,
<0x20004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
clocks = <&func_32k_ck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20000 0x1000>;
counter32k: counter@0 {
compatible = "ti,omap-counter32k";
reg = <0 0x20>;
};
};
};
@ -277,12 +290,33 @@
};
};
timer1: timer@49018000 {
compatible = "ti,omap2420-timer";
reg = <0x49018000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";
ti,timer-alwon;
timer1_target: target-module@49018000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x49018000 0x4>,
<0x49018010 0x4>,
<0x49018014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt1_fck>, <&gpt1_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49018000 0x1000>;
timer1: timer@0 {
compatible = "ti,omap2420-timer";
reg = <0 0x400>;
interrupts = <37>;
ti,timer-alwon;
};
};
mcspi3: spi@480b8000 {
@ -321,5 +355,15 @@
compatible = "ti,omap2430-i2c";
};
/include/ "omap24xx-clocks.dtsi"
/include/ "omap2430-clocks.dtsi"
#include "omap24xx-clocks.dtsi"
#include "omap2430-clocks.dtsi"
/* Preferred always-on timer for clockevent */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt1_fck>;
assigned-clock-parents = <&func_32k_ck>;
};
};

33
arch/arm/boot/dts/omap3-beagle.dts
View File

@ -304,6 +304,39 @@
phys = <0 &hsusb2_phy>;
};
/* Unusable as clocksource because of unreliable oscillator */
&counter32k {
status = "disabled";
};
/* Unusable as clockevent because if unreliable oscillator, allow to idle */
&timer1_target {
/delete-property/ti,no-reset-on-init;
/delete-property/ti,no-idle;
timer@0 {
/delete-property/ti,timer-alwon;
};
};
/* Preferred always-on timer for clocksource */
&timer12_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
/* Always clocked by secure_32k_fck */
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt2_fck>;
assigned-clock-parents = <&sys_ck>;
};
};
&twl_gpio {
ti,use-leds;
/* pullups: BIT(1) */

33
arch/arm/boot/dts/omap3-devkit8000.dts
View File

@ -14,3 +14,36 @@
display2 = &tv0;
};
};
/* Unusable as clocksource because of unreliable oscillator */
&counter32k {
status = "disabled";
};
/* Unusable as clockevent because if unreliable oscillator, allow to idle */
&timer1_target {
/delete-property/ti,no-reset-on-init;
/delete-property/ti,no-idle;
timer@0 {
/delete-property/ti,timer-alwon;
};
};
/* Preferred always-on timer for clocksource */
&timer12_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
/* Always clocked by secure_32k_fck */
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt2_fck>;
assigned-clock-parents = <&sys_ck>;
};
};

134
arch/arm/boot/dts/omap3.dtsi
View File

@ -193,10 +193,23 @@
};
};
counter32k: counter@48320000 {
compatible = "ti,omap-counter32k";
reg = <0x48320000 0x20>;
ti,hwmods = "counter_32k";
target-module@48320000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x48320000 0x4>,
<0x48320004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x48320000 0x1000>;
counter32k: counter@0 {
compatible = "ti,omap-counter32k";
reg = <0x0 0x20>;
};
};
intc: interrupt-controller@48200000 {
@ -637,19 +650,63 @@
dma-names = "rx";
};
timer1: timer@48318000 {
compatible = "ti,omap3430-timer";
reg = <0x48318000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";
ti,timer-alwon;
timer1_target: target-module@48318000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x48318000 0x4>,
<0x48318010 0x4>,
<0x48318014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt1_fck>, <&gpt1_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x48318000 0x1000>;
timer1: timer@0 {
compatible = "ti,omap3430-timer";
reg = <0x0 0x80>;
clocks = <&gpt1_fck>;
clock-names = "fck";
interrupts = <37>;
ti,timer-alwon;
};
};
timer2: timer@49032000 {
compatible = "ti,omap3430-timer";
reg = <0x49032000 0x400>;
interrupts = <38>;
ti,hwmods = "timer2";
timer2_target: target-module@49032000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x49032000 0x4>,
<0x49032010 0x4>,
<0x49032014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt2_fck>, <&gpt2_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49032000 0x1000>;
timer2: timer@0 {
compatible = "ti,omap3430-timer";
reg = <0 0x400>;
interrupts = <38>;
};
};
timer3: timer@49034000 {
@ -723,13 +780,34 @@
ti,timer-pwm;
};
timer12: timer@48304000 {
compatible = "ti,omap3430-timer";
reg = <0x48304000 0x400>;
interrupts = <95>;
ti,hwmods = "timer12";
ti,timer-alwon;
ti,timer-secure;
timer12_target: target-module@48304000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x48304000 0x4>,
<0x48304010 0x4>,
<0x48304014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt12_fck>, <&gpt12_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x48304000 0x1000>;
timer12: timer@0 {
compatible = "ti,omap3430-timer";
reg = <0 0x400>;
interrupts = <95>;
ti,timer-alwon;
ti,timer-secure;
};
};
usbhstll: usbhstll@48062000 {
@ -886,4 +964,14 @@
};
};
/include/ "omap3xxx-clocks.dtsi"
#include "omap3xxx-clocks.dtsi"
/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt1_fck>;
assigned-clock-parents = <&omap_32k_fck>;
};
};

4
arch/arm/boot/dts/omap4-l4.dtsi
View File

@ -974,7 +974,6 @@
target-module@4000 { /* 0x4a304000, ap 17 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@ -1139,9 +1138,8 @@
};
};
target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>,
<0x8014 0x4>;

10
arch/arm/boot/dts/omap4.dtsi
View File

@ -655,3 +655,13 @@
#reset-cells = <1>;
};
};
/* Preferred always-on timer for clockevent */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};

4
arch/arm/boot/dts/omap5-l4.dtsi
View File

@ -2150,7 +2150,6 @@
target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4010 0x4>;
reg-names = "rev", "sysc";
@ -2336,9 +2335,8 @@
};
};
target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>;
reg-names = "rev", "sysc";

10
arch/arm/boot/dts/omap5.dtsi
View File

@ -581,3 +581,13 @@
#reset-cells = <1>;
};
};
/* Preferred always-on timer for clockevent */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
assigned-clock-parents = <&sys_32k_ck>;
};
};

173
arch/arm/configs/cm_x2xx_defconfig
View File

@ -1,173 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_PXA=y
CONFIG_MACH_ARMCORE=y
CONFIG_PCI=y
CONFIG_PCCARD=m
CONFIG_YENTA=m
# CONFIG_YENTA_O2 is not set
# CONFIG_YENTA_RICOH is not set
# CONFIG_YENTA_ENE_TUNE is not set
# CONFIG_YENTA_TOSHIBA is not set
CONFIG_PCMCIA_PXA2XX=m
CONFIG_NO_HZ=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=1f03 mem=32M"
CONFIG_FPE_NWFPE=y
CONFIG_PM=y
CONFIG_APM_EMULATION=m
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_BT=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_BNEP=m
CONFIG_BT_HIDP=m
CONFIG_LIB80211=m
CONFIG_FW_LOADER=m
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PXA2XX=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPIO=m
CONFIG_MTD_NAND_CM_X270=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=m
# CONFIG_SATA_PMP is not set
CONFIG_PATA_PCMCIA=m
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_DM9000=y
CONFIG_DM9000_DEBUGLEVEL=1
CONFIG_NET_PCI=y
CONFIG_8139TOO=m
# CONFIG_8139TOO_PIO is not set
CONFIG_PPP=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_PXA27x=m
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_UCB1400=m
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_PXA=y
CONFIG_SPI=y
CONFIG_SPI_PXA2XX=m
# CONFIG_HWMON is not set
CONFIG_UCB1400_CORE=m
CONFIG_FB=y
CONFIG_FB_PXA=y
CONFIG_FB_PXA_PARAMETERS=y
CONFIG_FB_MBX=m
# CONFIG_LCD_CLASS_DEVICE is not set
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=m
CONFIG_SND=m
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_PCI is not set
CONFIG_SND_PXA2XX_AC97=m
# CONFIG_SND_SPI is not set
# CONFIG_SND_USB is not set
# CONFIG_SND_PCMCIA is not set
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_EZKEY=y
CONFIG_HID_GYRATION=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_PANTHERLORD=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
CONFIG_HID_SUNPLUS=y
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=m
CONFIG_MMC_PXA=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=m
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_V3020=y
CONFIG_RTC_DRV_PXA=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_VFAT_FS=m
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_CIFS=m
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_UTF8=m
CONFIG_FRAME_WARN=0
CONFIG_DEBUG_KERNEL=y
# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set

178
arch/arm/configs/em_x270_defconfig
View File

@ -1,178 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_PXA=y
CONFIG_MACH_EM_X270=y
CONFIG_MACH_EXEDA=y
CONFIG_NO_HZ=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=1f03 mem=32M"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_FPE_NWFPE=y
CONFIG_PM=y
CONFIG_APM_EMULATION=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_BT=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_BNEP=m
CONFIG_BT_HIDP=m
CONFIG_BT_HCIBTUSB=m
CONFIG_LIB80211=m
CONFIG_FW_LOADER=m
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PXA2XX=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_DM9000=y
CONFIG_DM9000_DEBUGLEVEL=1
CONFIG_PPP=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_APMPOWER=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_PXA27x=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_DA9034 is not set
CONFIG_TOUCHSCREEN_WM97XX=m
# CONFIG_TOUCHSCREEN_WM9705 is not set
# CONFIG_TOUCHSCREEN_WM9713 is not set
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_PXA=y
CONFIG_SPI=y
CONFIG_SPI_PXA2XX=y
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_DA9030=y
# CONFIG_HWMON is not set
CONFIG_PMIC_DA903X=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_DA903X=y
CONFIG_FB=y
CONFIG_FB_PXA=y
CONFIG_FB_PXA_PARAMETERS=y
CONFIG_FB_MBX=m
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_TDO24M=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_DA903X=m
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=m
CONFIG_SND=m
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_SPI is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=m
CONFIG_SND_PXA2XX_SOC=m
CONFIG_SND_PXA2XX_SOC_EM_X270=m
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_EZKEY=y
CONFIG_HID_GYRATION=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_HID_PANTHERLORD=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
CONFIG_HID_SUNPLUS=y
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=m
CONFIG_MMC_PXA=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_DA903X=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_V3020=y
CONFIG_RTC_DRV_PXA=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_VFAT_FS=m
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_CIFS=m
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_UTF8=m
CONFIG_FRAME_WARN=0
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_AES=m
CONFIG_CRYPTO_ARC4=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set

2
arch/arm/configs/pxa_defconfig
View File

@ -38,8 +38,6 @@ CONFIG_MACH_ARCOM_ZEUS=y
CONFIG_MACH_BALLOON3=y
CONFIG_MACH_CSB726=y
CONFIG_CSB726_CSB701=y
CONFIG_MACH_ARMCORE=y
CONFIG_MACH_EM_X270=y
CONFIG_MACH_EXEDA=y
CONFIG_MACH_CM_X300=y
CONFIG_MACH_CAPC7117=y

2
arch/arm/kernel/time.c
View File

@ -8,7 +8,6 @@
* This file contains the ARM-specific time handling details:
* reading the RTC at bootup, etc...
*/
#include <linux/clk-provider.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/errno.h>
@ -17,6 +16,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_clk.h>
#include <linux/profile.h>
#include <linux/sched.h>
#include <linux/sched_clock.h>

1
arch/arm/mach-actions/Kconfig
View File

@ -7,7 +7,6 @@ menuconfig ARCH_ACTIONS
select ARM_GLOBAL_TIMER
select CACHE_L2X0
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
select COMMON_CLK
select GENERIC_IRQ_CHIP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP

1
arch/arm/mach-alpine/Kconfig
View File

@ -7,7 +7,6 @@ config ARCH_ALPINE
select ARM_GIC
select GENERIC_IRQ_CHIP
select HAVE_ARM_ARCH_TIMER
select HAVE_SMP
select MFD_SYSCON
select FORCE_PCI
select PCI_HOST_GENERIC

1
arch/arm/mach-asm9260/Kconfig
View File

@ -4,6 +4,5 @@ config MACH_ASM9260
depends on ARCH_MULTI_V5
select CPU_ARM926T
select ASM9260_TIMER
select GENERIC_CLOCKEVENTS
help
Support for Alphascale ASM9260 based platform.

1
arch/arm/mach-aspeed/Kconfig
View File

@ -39,7 +39,6 @@ config MACH_ASPEED_G6
select PINCTRL_ASPEED_G6
select ARM_GIC
select HAVE_ARM_ARCH_TIMER
select HAVE_SMP
help
Say yes if you intend to run on an Aspeed ast2600 or similar
sixth generation Aspeed BMCs.

1
arch/arm/mach-berlin/Kconfig
View File

@ -19,7 +19,6 @@ config MACH_BERLIN_BG2
select CPU_PJ4B
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select PINCTRL_BERLIN_BG2
config MACH_BERLIN_BG2CD

5
arch/arm/mach-clps711x/Kconfig
View File

@ -2,15 +2,10 @@
menuconfig ARCH_CLPS711X
bool "Cirrus Logic EP721x/EP731x-based"
depends on ARCH_MULTI_V4T
select AUTO_ZRELADDR
select TIMER_OF
select CLPS711X_TIMER
select COMMON_CLK
select CPU_ARM720T
select GENERIC_CLOCKEVENTS
select GPIOLIB
select MFD_SYSCON
select OF_IRQ
select USE_OF
help
Select this if you use ARMv4T Cirrus Logic chips.

1
arch/arm/mach-davinci/Kconfig
View File

@ -64,7 +64,6 @@ config MACH_DA8XX_DT
default y
depends on ARCH_DAVINCI_DA850
select PINCTRL
select TIMER_OF
help
Say y here to include support for TI DaVinci DA850 based using
Flattened Device Tree. More information at Documentation/devicetree

26
arch/arm/mach-davinci/board-dm644x-evm.c
View File

@ -655,19 +655,6 @@ static struct i2c_board_info __initdata i2c_info[] = {
},
};
/* Fixed regulator support */
static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
/* Baseboard 3.3V: 5V -> TPS54310PWP -> 3.3V */
REGULATOR_SUPPLY("AVDD", "1-001b"),
REGULATOR_SUPPLY("DRVDD", "1-001b"),
};
static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
/* Baseboard 1.8V: 5V -> TPS54310PWP -> 1.8V */
REGULATOR_SUPPLY("IOVDD", "1-001b"),
REGULATOR_SUPPLY("DVDD", "1-001b"),
};
#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
@ -700,6 +687,19 @@ static void __init evm_init_i2c(void)
}
#endif
/* Fixed regulator support */
static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
/* Baseboard 3.3V: 5V -> TPS54310PWP -> 3.3V */
REGULATOR_SUPPLY("AVDD", "1-001b"),
REGULATOR_SUPPLY("DRVDD", "1-001b"),
};
static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
/* Baseboard 1.8V: 5V -> TPS54310PWP -> 1.8V */
REGULATOR_SUPPLY("IOVDD", "1-001b"),
REGULATOR_SUPPLY("DVDD", "1-001b"),
};
#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
/* venc standard timings */

1
arch/arm/mach-imx/common.h
View File

@ -49,7 +49,6 @@ void imx_aips_allow_unprivileged_access(const char *compat);
int mxc_device_init(void);
void imx_set_soc_revision(unsigned int rev);
void imx_init_revision_from_anatop(void);
struct device *imx_soc_device_init(void);
void imx6_enable_rbc(bool enable);
void imx_gpc_check_dt(void);
void imx_gpc_set_arm_power_in_lpm(bool power_off);

159
arch/arm/mach-imx/cpu.c
View File

@ -1,25 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/err.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include "hardware.h"
#include "common.h"
#define OCOTP_UID_H 0x420
#define OCOTP_UID_L 0x410
#define OCOTP_ULP_UID_1 0x4b0
#define OCOTP_ULP_UID_2 0x4c0
#define OCOTP_ULP_UID_3 0x4d0
#define OCOTP_ULP_UID_4 0x4e0
unsigned int __mxc_cpu_type;
static unsigned int imx_soc_revision;
@ -82,150 +70,3 @@ void __init imx_aips_allow_unprivileged_access(
imx_set_aips(aips_base_addr);
}
}
struct device * __init imx_soc_device_init(void)
{
struct soc_device_attribute *soc_dev_attr;
const char *ocotp_compat = NULL;
struct soc_device *soc_dev;
struct device_node *root;
struct regmap *ocotp = NULL;
const char *soc_id;
u64 soc_uid = 0;
u32 val;
int ret;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return NULL;
soc_dev_attr->family = "Freescale i.MX";
root = of_find_node_by_path("/");
ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
of_node_put(root);
if (ret)
goto free_soc;
switch (__mxc_cpu_type) {
case MXC_CPU_MX1:
soc_id = "i.MX1";
break;
case MXC_CPU_MX21:
soc_id = "i.MX21";
break;
case MXC_CPU_MX25:
soc_id = "i.MX25";
break;
case MXC_CPU_MX27:
soc_id = "i.MX27";
break;
case MXC_CPU_MX31:
soc_id = "i.MX31";
break;
case MXC_CPU_MX35:
soc_id = "i.MX35";
break;
case MXC_CPU_MX51:
soc_id = "i.MX51";
break;
case MXC_CPU_MX53:
soc_id = "i.MX53";
break;
case MXC_CPU_IMX6SL:
ocotp_compat = "fsl,imx6sl-ocotp";
soc_id = "i.MX6SL";
break;
case MXC_CPU_IMX6DL:
ocotp_compat = "fsl,imx6q-ocotp";
soc_id = "i.MX6DL";
break;
case MXC_CPU_IMX6SX:
ocotp_compat = "fsl,imx6sx-ocotp";
soc_id = "i.MX6SX";
break;
case MXC_CPU_IMX6Q:
ocotp_compat = "fsl,imx6q-ocotp";
soc_id = "i.MX6Q";
break;
case MXC_CPU_IMX6UL:
ocotp_compat = "fsl,imx6ul-ocotp";
soc_id = "i.MX6UL";
break;
case MXC_CPU_IMX6ULL:
ocotp_compat = "fsl,imx6ull-ocotp";
soc_id = "i.MX6ULL";
break;
case MXC_CPU_IMX6ULZ:
ocotp_compat = "fsl,imx6ull-ocotp";
soc_id = "i.MX6ULZ";
break;
case MXC_CPU_IMX6SLL:
ocotp_compat = "fsl,imx6sll-ocotp";
soc_id = "i.MX6SLL";
break;
case MXC_CPU_IMX7D:
ocotp_compat = "fsl,imx7d-ocotp";
soc_id = "i.MX7D";
break;
case MXC_CPU_IMX7ULP:
ocotp_compat = "fsl,imx7ulp-ocotp";
soc_id = "i.MX7ULP";
break;
default:
soc_id = "Unknown";
}
soc_dev_attr->soc_id = soc_id;
if (ocotp_compat) {
ocotp = syscon_regmap_lookup_by_compatible(ocotp_compat);
if (IS_ERR(ocotp))
pr_err("%s: failed to find %s regmap!\n", __func__, ocotp_compat);
}
if (!IS_ERR_OR_NULL(ocotp)) {
if (__mxc_cpu_type == MXC_CPU_IMX7ULP) {
regmap_read(ocotp, OCOTP_ULP_UID_4, &val);
soc_uid = val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_3, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_2, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_1, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
} else {
regmap_read(ocotp, OCOTP_UID_H, &val);
soc_uid = val;
regmap_read(ocotp, OCOTP_UID_L, &val);
soc_uid <<= 32;
soc_uid |= val;
}
}
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
(imx_soc_revision >> 4) & 0xf,
imx_soc_revision & 0xf);
if (!soc_dev_attr->revision)
goto free_soc;
soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
if (!soc_dev_attr->serial_number)
goto free_rev;
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev))
goto free_serial_number;
return soc_device_to_device(soc_dev);
free_serial_number:
kfree(soc_dev_attr->serial_number);
free_rev:
kfree(soc_dev_attr->revision);
free_soc:
kfree(soc_dev_attr);
return NULL;
}

8
arch/arm/mach-imx/mach-imx6q.c
View File

@ -245,21 +245,15 @@ static void __init imx6q_axi_init(void)
static void __init imx6q_init_machine(void)
{
struct device *parent;
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
else
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
imx_get_soc_revision());
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
imx6q_enet_phy_init();
of_platform_default_populate(NULL, NULL, parent);
of_platform_default_populate(NULL, NULL, NULL);
imx_anatop_init();
cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();

8
arch/arm/mach-imx/mach-imx6sl.c
View File

@ -45,13 +45,7 @@ static void __init imx6sl_init_late(void)
static void __init imx6sl_init_machine(void)
{
struct device *parent;
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
of_platform_default_populate(NULL, NULL, parent);
of_platform_default_populate(NULL, NULL, NULL);
if (cpu_is_imx6sl())
imx6sl_fec_init();

8
arch/arm/mach-imx/mach-imx6sx.c
View File

@ -63,13 +63,7 @@ static inline void imx6sx_enet_init(void)
static void __init imx6sx_init_machine(void)
{
struct device *parent;
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
of_platform_default_populate(NULL, NULL, parent);
of_platform_default_populate(NULL, NULL, NULL);
imx6sx_enet_init();
imx_anatop_init();

8
arch/arm/mach-imx/mach-imx6ul.c
View File

@ -55,13 +55,7 @@ static inline void imx6ul_enet_init(void)
static void __init imx6ul_init_machine(void)
{
struct device *parent;
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
of_platform_default_populate(NULL, NULL, parent);
of_platform_default_populate(NULL, NULL, NULL);
imx6ul_enet_init();
imx_anatop_init();
imx6ul_pm_init();

6
arch/arm/mach-imx/mach-imx7d.c
View File

@ -78,12 +78,6 @@ static inline void imx7d_enet_init(void)
static void __init imx7d_init_machine(void)
{
struct device *parent;
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
imx_anatop_init();
imx7d_enet_init();
}

2
arch/arm/mach-imx/mach-imx7ulp.c
View File

@ -57,7 +57,7 @@ static void __init imx7ulp_init_machine(void)
mxc_set_cpu_type(MXC_CPU_IMX7ULP);
imx7ulp_set_revision();
of_platform_default_populate(NULL, NULL, imx_soc_device_init());
of_platform_default_populate(NULL, NULL, NULL);
}
static const char *const imx7ulp_dt_compat[] __initconst = {

2
arch/arm/mach-imx/mach-pcm037.c
View File

@ -404,7 +404,7 @@ static struct resource pcm970_sja1000_resources[] = {
},
};
struct sja1000_platform_data pcm970_sja1000_platform_data = {
static struct sja1000_platform_data pcm970_sja1000_platform_data = {
.osc_freq = 16000000,
.ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
.cdr = CDR_CBP,

47
arch/arm/mach-imx/mach-vf610.c
View File

@ -3,11 +3,57 @@
* Copyright 2012-2013 Freescale Semiconductor, Inc.
*/
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>
#include "common.h"
#include "hardware.h"
#define MSCM_CPxCOUNT 0x00c
#define MSCM_CPxCFG1 0x014
static void __init vf610_detect_cpu(void)
{
struct device_node *np;
u32 cpxcount, cpxcfg1;
unsigned int cpu_type;
void __iomem *mscm;
np = of_find_compatible_node(NULL, NULL, "fsl,vf610-mscm-cpucfg");
if (WARN_ON(!np))
return;
mscm = of_iomap(np, 0);
of_node_put(np);
if (WARN_ON(!mscm))
return;
cpxcount = readl_relaxed(mscm + MSCM_CPxCOUNT);
cpxcfg1 = readl_relaxed(mscm + MSCM_CPxCFG1);
iounmap(mscm);
cpu_type = cpxcount ? MXC_CPU_VF600 : MXC_CPU_VF500;
if (cpxcfg1)
cpu_type |= MXC_CPU_VFx10;
mxc_set_cpu_type(cpu_type);
}
static void __init vf610_init_machine(void)
{
vf610_detect_cpu();
of_platform_default_populate(NULL, NULL, NULL);
}
static const char * const vf610_dt_compat[] __initconst = {
"fsl,vf500",
"fsl,vf510",
@ -20,5 +66,6 @@ static const char * const vf610_dt_compat[] __initconst = {
DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF5xx/VF6xx (Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_machine = vf610_init_machine,
.dt_compat = vf610_dt_compat,
MACHINE_END

22
arch/arm/mach-imx/mxc.h
View File

@ -8,35 +8,15 @@
#define __ASM_ARCH_MXC_H__
#include <linux/types.h>
#include <soc/imx/cpu.h>
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
#define MXC_CPU_MX1 1
#define MXC_CPU_MX21 21
#define MXC_CPU_MX25 25
#define MXC_CPU_MX27 27
#define MXC_CPU_MX31 31
#define MXC_CPU_MX35 35
#define MXC_CPU_MX51 51
#define MXC_CPU_MX53 53
#define MXC_CPU_IMX6SL 0x60
#define MXC_CPU_IMX6DL 0x61
#define MXC_CPU_IMX6SX 0x62
#define MXC_CPU_IMX6Q 0x63
#define MXC_CPU_IMX6UL 0x64
#define MXC_CPU_IMX6ULL 0x65
/* virtual cpu id for i.mx6ulz */
#define MXC_CPU_IMX6ULZ 0x6b
#define MXC_CPU_IMX6SLL 0x67
#define MXC_CPU_IMX7D 0x72
#define MXC_CPU_IMX7ULP 0xff
#define IMX_DDR_TYPE_LPDDR2 1
#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;
#ifdef CONFIG_SOC_IMX6SL
static inline bool cpu_is_imx6sl(void)

9
arch/arm/mach-integrator/Kconfig
View File

@ -3,7 +3,8 @@ menuconfig ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6
select ARM_AMBA
select COMMON_CLK_VERSATILE
select CMA
select DMA_CMA
select HAVE_TCM
select ICST
select MFD_SYSCON
@ -12,7 +13,6 @@ menuconfig ARCH_INTEGRATOR
select POWER_RESET_VERSATILE
select POWER_SUPPLY
select SOC_INTEGRATOR_CM
select SPARSE_IRQ
select VERSATILE_FPGA_IRQ
help
Support for ARM's Integrator platform.
@ -35,14 +35,13 @@ config INTEGRATOR_IMPD1
select ARM_VIC
select GPIO_PL061
select GPIOLIB
select REGULATOR
select REGULATOR_FIXED_VOLTAGE
help
The IM-PD1 is an add-on logic module for the Integrator which
allows ARM(R) Ltd PrimeCells to be developed and evaluated.
The IM-PD1 can be found on the Integrator/PP2 platform.
To compile this driver as a module, choose M here: the
module will be called impd1.
config INTEGRATOR_CM7TDMI
bool "Integrator/CM7TDMI core module"
depends on ARCH_INTEGRATOR_AP

3
arch/arm/mach-integrator/Makefile
View File

@ -5,7 +5,6 @@
# Object file lists.
obj-y := core.o lm.o
obj-y := core.o
obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o
obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o

475
arch/arm/mach-integrator/impd1.c
View File

@ -1,475 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-integrator/impd1.c
*
* Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
*
* This file provides the core support for the IM-PD1 module.
*
* Module / boot parameters.
* lmid=n impd1.lmid=n - set the logic module position in stack to 'n'
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/platform_data/clk-integrator.h>
#include <linux/slab.h>
#include <linux/irqchip/arm-vic.h>
#include <linux/gpio/machine.h>
#include <linux/sizes.h>
#include "lm.h"
#include "impd1.h"
static int module_id;
module_param_named(lmid, module_id, int, 0444);
MODULE_PARM_DESC(lmid, "logic module stack position");
struct impd1_module {
void __iomem *base;
void __iomem *vic_base;
};
void impd1_tweak_control(struct device *dev, u32 mask, u32 val)
{
struct impd1_module *impd1 = dev_get_drvdata(dev);
u32 cur;
val &= mask;
cur = readl(impd1->base + IMPD1_CTRL) & ~mask;
writel(cur | val, impd1->base + IMPD1_CTRL);
}
EXPORT_SYMBOL(impd1_tweak_control);
/*
* MMC support
*/
static struct mmci_platform_data mmc_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
};
/*
* CLCD support
*/
#define PANEL PROSPECTOR
#define LTM10C209 1
#define PROSPECTOR 2
#define SVGA 3
#define VGA 4
#if PANEL == VGA
#define PANELTYPE vga
static struct clcd_panel vga = {
.mode = {
.name = "VGA",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39721,
.left_margin = 40,
.right_margin = 24,
.upper_margin = 32,
.lower_margin = 11,
.hsync_len = 96,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
},
.width = -1,
.height = -1,
.tim2 = TIM2_BCD | TIM2_IPC,
.cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
.caps = CLCD_CAP_5551,
.connector = IMPD1_CTRL_DISP_VGA,
.bpp = 16,
.grayscale = 0,
};
#elif PANEL == SVGA
#define PANELTYPE svga
static struct clcd_panel svga = {
.mode = {
.name = "SVGA",
.refresh = 0,
.xres = 800,
.yres = 600,
.pixclock = 27778,
.left_margin = 20,
.right_margin = 20,
.upper_margin = 5,
.lower_margin = 5,
.hsync_len = 164,
.vsync_len = 62,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
},
.width = -1,
.height = -1,
.tim2 = TIM2_BCD,
.cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
.connector = IMPD1_CTRL_DISP_VGA,
.caps = CLCD_CAP_5551,
.bpp = 16,
.grayscale = 0,
};
#elif PANEL == PROSPECTOR
#define PANELTYPE prospector
static struct clcd_panel prospector = {
.mode = {
.name = "PROSPECTOR",
.refresh = 0,
.xres = 640,
.yres = 480,
.pixclock = 40000,
.left_margin = 33,
.right_margin = 64,
.upper_margin = 36,
.lower_margin = 7,
.hsync_len = 64,
.vsync_len = 25,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED,
},
.width = -1,
.height = -1,
.tim2 = TIM2_BCD,
.cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
.caps = CLCD_CAP_5551,
.fixedtimings = 1,
.connector = IMPD1_CTRL_DISP_LCD,
.bpp = 16,
.grayscale = 0,
};
#elif PANEL == LTM10C209
#define PANELTYPE ltm10c209
/*
* Untested.
*/
static struct clcd_panel ltm10c209 = {
.mode = {
.name = "LTM10C209",
.refresh = 0,
.xres = 640,
.yres = 480,
.pixclock = 40000,
.left_margin = 20,
.right_margin = 20,
.upper_margin = 19,
.lower_margin = 19,
.hsync_len = 20,
.vsync_len = 10,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED,
},
.width = -1,
.height = -1,
.tim2 = TIM2_BCD,
.cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
.caps = CLCD_CAP_5551,
.fixedtimings = 1,
.connector = IMPD1_CTRL_DISP_LCD,
.bpp = 16,
.grayscale = 0,
};
#endif
/*
* Disable all display connectors on the interface module.
*/
static void impd1fb_clcd_disable(struct clcd_fb *fb)
{
impd1_tweak_control(fb->dev->dev.parent, IMPD1_CTRL_DISP_MASK, 0);
}
/*
* Enable the relevant connector on the interface module.
*/
static void impd1fb_clcd_enable(struct clcd_fb *fb)
{
impd1_tweak_control(fb->dev->dev.parent, IMPD1_CTRL_DISP_MASK,
fb->panel->connector | IMPD1_CTRL_DISP_ENABLE);
}
static int impd1fb_clcd_setup(struct clcd_fb *fb)
{
unsigned long framebase = fb->dev->res.start + 0x01000000;
unsigned long framesize = SZ_1M;
int ret = 0;
fb->panel = &PANELTYPE;
if (!request_mem_region(framebase, framesize, "clcd framebuffer")) {
printk(KERN_ERR "IM-PD1: unable to reserve framebuffer\n");
return -EBUSY;
}
fb->fb.screen_base = ioremap(framebase, framesize);
if (!fb->fb.screen_base) {
printk(KERN_ERR "IM-PD1: unable to map framebuffer\n");
ret = -ENOMEM;
goto free_buffer;
}
fb->fb.fix.smem_start = framebase;
fb->fb.fix.smem_len = framesize;
return 0;
free_buffer:
release_mem_region(framebase, framesize);
return ret;
}
static int impd1fb_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
unsigned long start, size;
start = vma->vm_pgoff + (fb->fb.fix.smem_start >> PAGE_SHIFT);
size = vma->vm_end - vma->vm_start;
return remap_pfn_range(vma, vma->vm_start, start, size,
vma->vm_page_prot);
}
static void impd1fb_clcd_remove(struct clcd_fb *fb)
{
iounmap(fb->fb.screen_base);
release_mem_region(fb->fb.fix.smem_start, fb->fb.fix.smem_len);
}
static struct clcd_board impd1_clcd_data = {
.name = "IM-PD/1",
.caps = CLCD_CAP_5551 | CLCD_CAP_888,
.check = clcdfb_check,
.decode = clcdfb_decode,
.disable = impd1fb_clcd_disable,
.enable = impd1fb_clcd_enable,
.setup = impd1fb_clcd_setup,
.mmap = impd1fb_clcd_mmap,
.remove = impd1fb_clcd_remove,
};
struct impd1_device {
unsigned long offset;
unsigned int irq[2];
unsigned int id;
void *platform_data;
};
static struct impd1_device impd1_devs[] = {
{
.offset = 0x00100000,
.irq = { 1 },
.id = 0x00141011,
}, {
.offset = 0x00200000,
.irq = { 2 },
.id = 0x00141011,
}, {
.offset = 0x00300000,
.irq = { 3 },
.id = 0x00041022,
}, {
.offset = 0x00400000,
.irq = { 4 },
.id = 0x00041061,
}, {
.offset = 0x00500000,
.irq = { 5 },
.id = 0x00041061,
}, {
.offset = 0x00600000,
.irq = { 6 },
.id = 0x00041130,
}, {
.offset = 0x00700000,
.irq = { 7, 8 },
.id = 0x00041181,
.platform_data = &mmc_data,
}, {
.offset = 0x00800000,
.irq = { 9 },
.id = 0x00041041,
}, {
.offset = 0x01000000,
.irq = { 11 },
.id = 0x00041110,
.platform_data = &impd1_clcd_data,
}
};
/*
* Valid IRQs: 0 thru 9 and 11, 10 unused.
*/
#define IMPD1_VALID_IRQS 0x00000bffU
/*
* As this module is bool, it is OK to have this as __ref() - no
* probe calls will be done after the initial system bootup, as devices
* are discovered as part of the machine startup.
*/
static int __ref impd1_probe(struct lm_device *dev)
{
struct impd1_module *impd1;
int irq_base;
int i;
if (dev->id != module_id)
return -EINVAL;
if (!devm_request_mem_region(&dev->dev, dev->resource.start,
SZ_4K, "LM registers"))
return -EBUSY;
impd1 = devm_kzalloc(&dev->dev, sizeof(struct impd1_module),
GFP_KERNEL);
if (!impd1)
return -ENOMEM;
impd1->base = devm_ioremap(&dev->dev, dev->resource.start, SZ_4K);
if (!impd1->base)
return -ENOMEM;
integrator_impd1_clk_init(impd1->base, dev->id);
if (!devm_request_mem_region(&dev->dev,
dev->resource.start + 0x03000000,
SZ_4K, "VIC"))
return -EBUSY;
impd1->vic_base = devm_ioremap(&dev->dev,
dev->resource.start + 0x03000000,
SZ_4K);
if (!impd1->vic_base)
return -ENOMEM;
irq_base = vic_init_cascaded(impd1->vic_base, dev->irq,
IMPD1_VALID_IRQS, 0);
lm_set_drvdata(dev, impd1);
dev_info(&dev->dev, "IM-PD1 found at 0x%08lx\n",
(unsigned long)dev->resource.start);
for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) {
struct impd1_device *idev = impd1_devs + i;
struct amba_device *d;
unsigned long pc_base;
char devname[32];
int irq1 = idev->irq[0];
int irq2 = idev->irq[1];
/* Translate IRQs to IM-PD1 local numberspace */
if (irq1)
irq1 += irq_base;
if (irq2)
irq2 += irq_base;
pc_base = dev->resource.start + idev->offset;
snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
/* Add GPIO descriptor lookup table for the PL061 block */
if (idev->offset == 0x00400000) {
struct gpiod_lookup_table *lookup;
char *chipname;
char *mmciname;
lookup = devm_kzalloc(&dev->dev,
struct_size(lookup, table, 3),
GFP_KERNEL);
chipname = devm_kstrdup(&dev->dev, devname, GFP_KERNEL);
mmciname = devm_kasprintf(&dev->dev, GFP_KERNEL,
"lm%x:00700", dev->id);
if (!lookup || !chipname || !mmciname)
return -ENOMEM;
lookup->dev_id = mmciname;
/*
* Offsets on GPIO block 1:
* 3 = MMC WP (write protect)
* 4 = MMC CD (card detect)
*
* Offsets on GPIO block 2:
* 0 = Up key
* 1 = Down key
* 2 = Left key
* 3 = Right key
* 4 = Key lower left
* 5 = Key lower right
*/
/* We need the two MMCI GPIO entries */
lookup->table[0] = (struct gpiod_lookup)
GPIO_LOOKUP(chipname, 3, "wp", 0);
lookup->table[1] = (struct gpiod_lookup)
GPIO_LOOKUP(chipname, 4, "cd", GPIO_ACTIVE_LOW);
gpiod_add_lookup_table(lookup);
}
d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K,
irq1, irq2,
idev->platform_data, idev->id,
&dev->resource);
if (IS_ERR(d)) {
dev_err(&dev->dev, "unable to register device: %ld\n", PTR_ERR(d));
continue;
}
}
return 0;
}
static int impd1_remove_one(struct device *dev, void *data)
{
device_unregister(dev);
return 0;
}
static void impd1_remove(struct lm_device *dev)
{
device_for_each_child(&dev->dev, NULL, impd1_remove_one);
integrator_impd1_clk_exit(dev->id);
lm_set_drvdata(dev, NULL);
}
static struct lm_driver impd1_driver = {
.drv = {
.name = "impd1",
/*
* As we're dropping the probe() function, suppress driver
* binding from sysfs.
*/
.suppress_bind_attrs = true,
},
.probe = impd1_probe,
.remove = impd1_remove,
};
static int __init impd1_init(void)
{
return lm_driver_register(&impd1_driver);
}
static void __exit impd1_exit(void)
{
lm_driver_unregister(&impd1_driver);
}
module_init(impd1_init);
module_exit(impd1_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Integrator/IM-PD1 logic module core driver");
MODULE_AUTHOR("Deep Blue Solutions Ltd");

15
arch/arm/mach-integrator/impd1.h
View File

@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#define IMPD1_LEDS 0x0c
#define IMPD1_INT 0x10
#define IMPD1_SW 0x14
#define IMPD1_CTRL 0x18
#define IMPD1_CTRL_DISP_LCD (0 << 0)
#define IMPD1_CTRL_DISP_VGA (1 << 0)
#define IMPD1_CTRL_DISP_LCD1 (2 << 0)
#define IMPD1_CTRL_DISP_ENABLE (1 << 2)
#define IMPD1_CTRL_DISP_MASK (7 << 0)
struct device;
void impd1_tweak_control(struct device *dev, u32 mask, u32 val);

31
arch/arm/mach-integrator/integrator_ap.c
View File

@ -23,7 +23,6 @@
#include "hardware.h"
#include "cm.h"
#include "common.h"
#include "lm.h"
/* Regmap to the AP system controller */
static struct regmap *ap_syscon_map;
@ -174,10 +173,7 @@ static const struct of_device_id ap_syscon_match[] = {
static void __init ap_init_of(void)
{
u32 sc_dec;
struct device_node *syscon;
int ret;
int i;
of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
@ -189,33 +185,6 @@ static void __init ap_init_of(void)
pr_crit("could not find Integrator/AP system controller\n");
return;
}
ret = regmap_read(ap_syscon_map,
INTEGRATOR_SC_DEC_OFFSET,
&sc_dec);
if (ret) {
pr_crit("could not read from Integrator/AP syscon\n");
return;
}
for (i = 0; i < 4; i++) {
struct lm_device *lmdev;
if ((sc_dec & (16 << i)) == 0)
continue;
lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
if (!lmdev)
continue;
lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
lmdev->resource.flags = IORESOURCE_MEM;
lmdev->irq = irq_of_parse_and_map(syscon, i);
lmdev->id = i;
lm_device_register(lmdev);
}
}
static const char * ap_dt_board_compat[] = {

96
arch/arm/mach-integrator/lm.c
View File

@ -1,96 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-integrator/lm.c
*
* Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/slab.h>
#include "lm.h"
#define to_lm_device(d) container_of(d, struct lm_device, dev)
#define to_lm_driver(d) container_of(d, struct lm_driver, drv)
static int lm_match(struct device *dev, struct device_driver *drv)
{
return 1;
}
static int lm_bus_probe(struct device *dev)
{
struct lm_device *lmdev = to_lm_device(dev);
struct lm_driver *lmdrv = to_lm_driver(dev->driver);
return lmdrv->probe(lmdev);
}
static int lm_bus_remove(struct device *dev)
{
struct lm_device *lmdev = to_lm_device(dev);
struct lm_driver *lmdrv = to_lm_driver(dev->driver);
if (lmdrv->remove)
lmdrv->remove(lmdev);
return 0;
}
static struct bus_type lm_bustype = {
.name = "logicmodule",
.match = lm_match,
.probe = lm_bus_probe,
.remove = lm_bus_remove,
// .suspend = lm_bus_suspend,
// .resume = lm_bus_resume,
};
static int __init lm_init(void)
{
return bus_register(&lm_bustype);
}
postcore_initcall(lm_init);
int lm_driver_register(struct lm_driver *drv)
{
drv->drv.bus = &lm_bustype;
return driver_register(&drv->drv);
}
void lm_driver_unregister(struct lm_driver *drv)
{
driver_unregister(&drv->drv);
}
static void lm_device_release(struct device *dev)
{
struct lm_device *d = to_lm_device(dev);
kfree(d);
}
int lm_device_register(struct lm_device *dev)
{
int ret;
dev->dev.release = lm_device_release;
dev->dev.bus = &lm_bustype;
ret = dev_set_name(&dev->dev, "lm%d", dev->id);
if (ret)
return ret;
dev->resource.name = dev_name(&dev->dev);
ret = request_resource(&iomem_resource, &dev->resource);
if (ret == 0) {
ret = device_register(&dev->dev);
if (ret)
release_resource(&dev->resource);
}
return ret;
}
EXPORT_SYMBOL(lm_driver_register);
EXPORT_SYMBOL(lm_driver_unregister);

24
arch/arm/mach-integrator/lm.h
View File

@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
struct lm_device {
struct device dev;
struct resource resource;
unsigned int irq;
unsigned int id;
};
struct lm_driver {
struct device_driver drv;
int (*probe)(struct lm_device *);
void (*remove)(struct lm_device *);
int (*suspend)(struct lm_device *, pm_message_t);
int (*resume)(struct lm_device *);
};
int lm_driver_register(struct lm_driver *drv);
void lm_driver_unregister(struct lm_driver *drv);
int lm_device_register(struct lm_device *dev);
#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)

2
arch/arm/mach-mediatek/mediatek.c
View File

@ -9,7 +9,7 @@
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/of_clk.h>
#include <linux/clocksource.h>

1
arch/arm/mach-mmp/Kconfig
View File

@ -110,7 +110,6 @@ config MACH_MMP_DT
depends on ARCH_MULTI_V5
select PINCTRL
select PINCTRL_SINGLE
select COMMON_CLK
select ARCH_HAS_RESET_CONTROLLER
select CPU_MOHAWK
help

2
arch/arm/mach-mmp/mmp-dt.c
View File

@ -8,7 +8,7 @@
#include <linux/irqchip.h>
#include <linux/of_platform.h>
#include <linux/clk-provider.h>
#include <linux/of_clk.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>

2
arch/arm/mach-mmp/mmp2-dt.c
View File

@ -9,7 +9,7 @@
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/of_platform.h>
#include <linux/clk-provider.h>
#include <linux/of_clk.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>

3
arch/arm/mach-mvebu/Kconfig
View File

@ -47,7 +47,6 @@ config MACH_ARMADA_375
select ARMADA_375_CLK
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_375
help
@ -66,7 +65,6 @@ config MACH_ARMADA_38X
select ARMADA_38X_CLK
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_38X
help
@ -82,7 +80,6 @@ config MACH_ARMADA_39X
select CACHE_L2X0
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_39X
help

1
arch/arm/mach-omap2/Kconfig
View File

@ -66,7 +66,6 @@ config SOC_AM43XX
select ARCH_OMAP2PLUS
select ARM_GIC
select MACH_OMAP_GENERIC
select MIGHT_HAVE_CACHE_L2X0
select HAVE_ARM_SCU
select GENERIC_CLOCKEVENTS_BROADCAST
select HAVE_ARM_TWD

6
arch/arm/mach-omap2/Makefile
View File

@ -7,7 +7,7 @@ ccflags-y := -I$(srctree)/$(src)/include \
-I$(srctree)/arch/arm/plat-omap/include
# Common support
obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \
obj-y := id.o io.o control.o devices.o fb.o pm.o \
common.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
omap_device.o omap-headsmp.o sram.o
@ -46,6 +46,10 @@ obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o
obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o
omap5-dra7-common-$(CONFIG_SOC_HAS_REALTIME_COUNTER) = timer.o
obj-$(CONFIG_SOC_OMAP5) += $(omap5-dra7-common-y)
obj-$(CONFIG_SOC_DRA7XX) += $(omap5-dra7-common-y)
# Functions loaded to SRAM
obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
obj-$(CONFIG_SOC_OMAP2430) += sram243x.o

39
arch/arm/mach-omap2/board-generic.c
View File

@ -12,6 +12,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/irqdomain.h>
#include <linux/clocksource.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
@ -31,6 +32,20 @@ static void __init __maybe_unused omap_generic_init(void)
omap_soc_device_init();
}
/* Clocks are needed early, see drivers/clocksource for the rest */
void __init __maybe_unused omap_init_time_of(void)
{
omap_clk_init();
timer_probe();
}
/* Used by am437x for ARM timer in non-SMP configurations */
#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
void tick_broadcast(const struct cpumask *mask)
{
}
#endif
#ifdef CONFIG_SOC_OMAP2420
static const char *const omap242x_boards_compat[] __initconst = {
"ti,omap2420",
@ -42,7 +57,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_machine = omap_generic_init,
.init_time = omap_init_time,
.init_time = omap_init_time_of,
.dt_compat = omap242x_boards_compat,
.restart = omap2xxx_restart,
MACHINE_END
@ -59,7 +74,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_machine = omap_generic_init,
.init_time = omap_init_time,
.init_time = omap_init_time_of,
.dt_compat = omap243x_boards_compat,
.restart = omap2xxx_restart,
MACHINE_END
@ -106,7 +121,7 @@ DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap_init_time,
.init_time = omap_init_time_of,
.dt_compat = n900_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@ -124,7 +139,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap_init_time,
.init_time = omap_init_time_of,
.dt_compat = omap3_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@ -141,7 +156,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
.init_early = omap3630_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap_init_time,
.init_time = omap_init_time_of,
.dt_compat = omap36xx_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@ -158,7 +173,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap3_secure_sync32k_timer_init,
.init_time = omap_init_time_of,
.dt_compat = omap3_gp_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@ -174,7 +189,7 @@ DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
.init_early = am35xx_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap3_gptimer_timer_init,
.init_time = omap_init_time_of,
.dt_compat = am3517_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@ -193,7 +208,7 @@ DT_MACHINE_START(TI814X_DT, "Generic ti814x (Flattened Device Tree)")
.init_early = ti814x_init_early,
.init_machine = omap_generic_init,
.init_late = ti81xx_init_late,
.init_time = omap3_gptimer_timer_init,
.init_time = omap_init_time_of,
.dt_compat = ti814x_boards_compat,
.restart = ti81xx_restart,
MACHINE_END
@ -210,7 +225,7 @@ DT_MACHINE_START(TI816X_DT, "Generic ti816x (Flattened Device Tree)")
.init_early = ti816x_init_early,
.init_machine = omap_generic_init,
.init_late = ti81xx_init_late,
.init_time = omap3_gptimer_timer_init,
.init_time = omap_init_time_of,
.dt_compat = ti816x_boards_compat,
.restart = ti81xx_restart,
MACHINE_END
@ -228,7 +243,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
.init_early = am33xx_init_early,
.init_machine = omap_generic_init,
.init_late = am33xx_init_late,
.init_time = omap3_gptimer_timer_init,
.init_time = omap_init_time_of,
.dt_compat = am33xx_boards_compat,
.restart = am33xx_restart,
MACHINE_END
@ -253,7 +268,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
.init_late = omap4430_init_late,
.init_time = omap4_local_timer_init,
.init_time = omap_init_time_of,
.dt_compat = omap4_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
@ -300,7 +315,7 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
.init_late = am43xx_init_late,
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
.init_time = omap3_gptimer_timer_init,
.init_time = omap_init_time_of,
.dt_compat = am43_boards_compat,
.restart = omap44xx_restart,
MACHINE_END

7
arch/arm/mach-omap2/common.h
View File

@ -111,7 +111,14 @@ static inline int omap_l2_cache_init(void)
#define OMAP_L2C_AUX_CTRL 0
#define omap4_l2c310_write_sec NULL
#endif
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
extern void omap5_realtime_timer_init(void);
#else
static inline void omap5_realtime_timer_init(void)
{
}
#endif
void omap2420_init_early(void);
void omap2430_init_early(void);

2
arch/arm/mach-omap2/omap-smp.c
View File

@ -72,7 +72,7 @@ void __iomem *omap4_get_scu_base(void)
}
#ifdef CONFIG_OMAP5_ERRATA_801819
void omap5_erratum_workaround_801819(void)
static void omap5_erratum_workaround_801819(void)
{
u32 acr, revidr;
u32 acr_mask;

20
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@ -264,14 +264,6 @@ static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
.master = &omap2xxx_l4_wkup_hwmod,
.slave = &omap2xxx_timer1_hwmod,
.clk = "gpt1_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
.master = &omap2xxx_l4_wkup_hwmod,
@ -352,15 +344,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
/* l4_wkup -> 32ksync_counter */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
.master = &omap2xxx_l4_wkup_hwmod,
.slave = &omap2xxx_counter_32k_hwmod,
.clk = "sync_32k_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
.master = &omap2xxx_l3_main_hwmod,
.slave = &omap2xxx_gpmc_hwmod,
@ -382,8 +365,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
&omap2420_l4_core__i2c2,
&omap2420_l3__iva,
&omap2420_l3__dsp,
&omap2420_l4_wkup__timer1,
&omap2xxx_l4_core__timer2,
&omap2xxx_l4_core__timer3,
&omap2xxx_l4_core__timer4,
&omap2xxx_l4_core__timer5,
@ -411,7 +392,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
&omap2xxx_l4_core__sham,
&omap2xxx_l4_core__aes,
&omap2420_l4_core__hdq1w,
&omap2420_l4_wkup__counter_32k,
&omap2420_l3__gpmc,
NULL,
};

19
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

@ -436,14 +436,6 @@ static struct omap_hwmod_ocp_if omap2430_l3__iva = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
.master = &omap2xxx_l4_wkup_hwmod,
.slave = &omap2xxx_timer1_hwmod,
.clk = "gpt1_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
.master = &omap2xxx_l4_wkup_hwmod,
@ -548,14 +540,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
/* l4_wkup -> 32ksync_counter */
static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
.master = &omap2xxx_l4_wkup_hwmod,
.slave = &omap2xxx_counter_32k_hwmod,
.clk = "sync_32k_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
.master = &omap2xxx_l3_main_hwmod,
.slave = &omap2xxx_gpmc_hwmod,
@ -581,8 +565,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
&omap2xxx_l4_core__mcspi2,
&omap2430_l4_core__mcspi3,
&omap2430_l3__iva,
&omap2430_l4_wkup__timer1,
&omap2xxx_l4_core__timer2,
&omap2xxx_l4_core__timer3,
&omap2xxx_l4_core__timer4,
&omap2xxx_l4_core__timer5,
@ -613,7 +595,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
&omap2xxx_l4_core__rng,
&omap2xxx_l4_core__sham,
&omap2xxx_l4_core__aes,
&omap2430_l4_wkup__counter_32k,
&omap2430_l3__gpmc,
NULL,
};

8
arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
View File

@ -95,14 +95,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> timer2 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
.master = &omap2xxx_l4_core_hwmod,
.slave = &omap2xxx_timer2_hwmod,
.clk = "gpt2_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> timer3 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
.master = &omap2xxx_l4_core_hwmod,

47
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
View File

@ -195,36 +195,6 @@ struct omap_hwmod omap2xxx_iva_hwmod = {
.class = &iva_hwmod_class,
};
/* timer1 */
struct omap_hwmod omap2xxx_timer1_hwmod = {
.name = "timer1",
.main_clk = "gpt1_fck",
.prcm = {
.omap2 = {
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
},
},
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer2 */
struct omap_hwmod omap2xxx_timer2_hwmod = {
.name = "timer2",
.main_clk = "gpt2_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
},
},
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer3 */
struct omap_hwmod omap2xxx_timer3_hwmod = {
.name = "timer3",
@ -595,23 +565,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
.class = &omap2xxx_mcspi_class,
};
static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
.name = "counter",
};
struct omap_hwmod omap2xxx_counter_32k_hwmod = {
.name = "counter_32k",
.main_clk = "func_32k_ck",
.prcm = {
.omap2 = {
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
},
},
.class = &omap2xxx_counter_hwmod_class,
};
/* gpmc */
struct omap_hwmod omap2xxx_gpmc_hwmod = {
.name = "gpmc",

2
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
View File

@ -44,8 +44,6 @@ extern struct omap_hwmod am33xx_smartreflex0_hwmod;
extern struct omap_hwmod am33xx_smartreflex1_hwmod;
extern struct omap_hwmod am33xx_gpmc_hwmod;
extern struct omap_hwmod am33xx_rtc_hwmod;
extern struct omap_hwmod am33xx_timer1_hwmod;
extern struct omap_hwmod am33xx_timer2_hwmod;
extern struct omap_hwmod_class am33xx_emif_hwmod_class;
extern struct omap_hwmod_class am33xx_l4_hwmod_class;

8
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View File

@ -106,14 +106,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.user = OCP_USER_MPU,
};
/* l4 per -> timer2 */
struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer2_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l3 main -> ocmc */
struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
.master = &am33xx_l3_main_hwmod,

62
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View File

@ -307,72 +307,12 @@ struct omap_hwmod am33xx_rtc_hwmod = {
},
};
/* 'timer 2-7' class */
static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_RESET_STATUS,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
struct omap_hwmod_class am33xx_timer_hwmod_class = {
.name = "timer",
.sysc = &am33xx_timer_sysc,
};
/* timer1 1ms */
static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
.name = "timer",
.sysc = &am33xx_timer1ms_sysc,
};
struct omap_hwmod am33xx_timer1_hwmod = {
.name = "timer1",
.class = &am33xx_timer1ms_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.main_clk = "timer1_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
struct omap_hwmod am33xx_timer2_hwmod = {
.name = "timer2",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "timer2_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static void omap_hwmod_am33xx_clkctrl(void)
{
CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex0_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex1_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
@ -399,12 +339,10 @@ void omap_hwmod_am33xx_reg(void)
static void omap_hwmod_am43xx_clkctrl(void)
{
CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex0_hwmod,
AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex1_hwmod,
AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);

10
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View File

@ -265,14 +265,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
.user = OCP_USER_MPU,
};
/* l4 wkup -> timer1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_timer1_hwmod,
.clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__emif,
&am33xx_mpu__l3_main,
@ -291,9 +283,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__control,
&am33xx_l4_wkup__smartreflex0,
&am33xx_l4_wkup__smartreflex1,
&am33xx_l4_wkup__timer1,
&am33xx_l4_wkup__rtc,
&am33xx_l4_ls__timer2,
&am33xx_l3_s__gpmc,
&am33xx_l3_main__ocmc,
NULL,

146
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -147,36 +147,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
.sysc = &omap3xxx_timer_sysc,
};
/* timer1 */
static struct omap_hwmod omap3xxx_timer1_hwmod = {
.name = "timer1",
.main_clk = "gpt1_fck",
.prcm = {
.omap2 = {
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
},
},
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer2 */
static struct omap_hwmod omap3xxx_timer2_hwmod = {
.name = "timer2",
.main_clk = "gpt2_fck",
.prcm = {
.omap2 = {
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
},
},
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer3 */
static struct omap_hwmod omap3xxx_timer3_hwmod = {
.name = "timer3",
@ -312,21 +282,6 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer12 */
static struct omap_hwmod omap3xxx_timer12_hwmod = {
.name = "timer12",
.main_clk = "gpt12_fck",
.prcm = {
.omap2 = {
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
},
},
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
@ -1524,38 +1479,6 @@ static struct omap_hwmod omap3xxx_sad2d_hwmod = {
.class = &omap3xxx_sad2d_class,
};
/*
* '32K sync counter' class
* 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
*/
static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0004,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
.name = "counter",
.sysc = &omap3xxx_counter_sysc,
};
static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
.name = "counter_32k",
.class = &omap3xxx_counter_hwmod_class,
.clkdm_name = "wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "wkup_32k_fck",
.prcm = {
.omap2 = {
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
},
},
};
/*
* 'gpmc' class
* general purpose memory controller
@ -1868,25 +1791,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
.master = &omap3xxx_l4_wkup_hwmod,
.slave = &omap3xxx_timer1_hwmod,
.clk = "gpt1_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> timer2 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
.master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_timer2_hwmod,
.clk = "gpt2_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per -> timer3 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
.master = &omap3xxx_l4_per_hwmod,
@ -1965,15 +1869,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> timer12 */
static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
.master = &omap3xxx_l4_sec_hwmod,
.slave = &omap3xxx_timer12_hwmod,
.clk = "gpt12_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
@ -2325,16 +2220,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
/* l4_wkup -> 32ksync_counter */
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
.master = &omap3xxx_l4_wkup_hwmod,
.slave = &omap3xxx_counter_32k_hwmod,
.clk = "omap_32ksync_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* am35xx has Davinci MDIO & EMAC */
static struct omap_hwmod_class am35xx_mdio_class = {
.name = "davinci_mdio",
@ -2551,8 +2436,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
&omap3_l4_core__i2c2,
&omap3_l4_core__i2c3,
&omap3xxx_l4_wkup__l4_sec,
&omap3xxx_l4_wkup__timer1,
&omap3xxx_l4_per__timer2,
&omap3xxx_l4_per__timer3,
&omap3xxx_l4_per__timer4,
&omap3xxx_l4_per__timer5,
@ -2580,27 +2463,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
&omap34xx_l4_core__mcspi2,
&omap34xx_l4_core__mcspi3,
&omap34xx_l4_core__mcspi4,
&omap3xxx_l4_wkup__counter_32k,
&omap3xxx_l3_main__gpmc,
NULL,
};
/* GP-only hwmod links */
static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12,
NULL,
};
static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12,
NULL,
};
static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12,
NULL,
};
/* crypto hwmod links */
static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__sham,
@ -2774,7 +2640,7 @@ static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
int __init omap3xxx_hwmod_init(void)
{
int r;
struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL;
struct omap_hwmod_ocp_if **h_aes = NULL;
struct device_node *bus;
unsigned int rev;
@ -2797,18 +2663,15 @@ int __init omap3xxx_hwmod_init(void)
rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
h = omap34xx_hwmod_ocp_ifs;
h_gp = omap34xx_gp_hwmod_ocp_ifs;
h_sham = omap34xx_sham_hwmod_ocp_ifs;
h_aes = omap34xx_aes_hwmod_ocp_ifs;
} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
h = am35xx_hwmod_ocp_ifs;
h_gp = am35xx_gp_hwmod_ocp_ifs;
h_sham = am35xx_sham_hwmod_ocp_ifs;
h_aes = am35xx_aes_hwmod_ocp_ifs;
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
rev == OMAP3630_REV_ES1_2) {
h = omap36xx_hwmod_ocp_ifs;
h_gp = omap36xx_gp_hwmod_ocp_ifs;
h_sham = omap36xx_sham_hwmod_ocp_ifs;
h_aes = omap36xx_aes_hwmod_ocp_ifs;
} else {
@ -2820,13 +2683,6 @@ int __init omap3xxx_hwmod_init(void)
if (r < 0)
return r;
/* Register GP-only hwmod links. */
if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
r = omap_hwmod_register_links(h_gp);
if (r < 0)
return r;
}
/*
* Register crypto hwmod links only if they are not disabled in DT.
* If DT information is missing, enable them only for GP devices.

45
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View File

@ -85,34 +85,6 @@ static struct omap_hwmod am43xx_control_hwmod = {
},
};
static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x4,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
.name = "synctimer",
.sysc = &am43xx_synctimer_sysc,
};
static struct omap_hwmod am43xx_synctimer_hwmod = {
.name = "counter_32k",
.class = &am43xx_synctimer_hwmod_class,
.clkdm_name = "l4_wkup_aon_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "synctimer_32kclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
@ -206,20 +178,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_timer1_hwmod,
.clk = "sys_clkin_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am43xx_synctimer_hwmod,
.clk = "sys_clkin_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
.master = &am33xx_l3_s_hwmod,
.slave = &am43xx_usb_otg_ss0_hwmod,
@ -235,7 +193,6 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
};
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__synctimer,
&am33xx_mpu__l3_main,
&am33xx_mpu__prcm,
&am33xx_l3_s__l4_ls,
@ -252,8 +209,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am43xx_l4_wkup__control,
&am43xx_l4_wkup__smartreflex0,
&am43xx_l4_wkup__smartreflex1,
&am43xx_l4_wkup__timer1,
&am33xx_l4_ls__timer2,
&am33xx_l3_s__gpmc,
&am33xx_l3_main__ocmc,
&am43xx_l3_s__usbotgss0,

90
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -231,39 +231,6 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
* usim
*/
/*
* 'counter' class
* 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
*/
static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0004,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
.name = "counter",
.sysc = &omap44xx_counter_sysc,
};
/* counter_32k */
static struct omap_hwmod omap44xx_counter_32k_hwmod = {
.name = "counter_32k",
.class = &omap44xx_counter_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
},
},
};
/*
* 'ctrl_module' class
* attila core control module + core pad control module + wkup pad control
@ -672,45 +639,6 @@ static struct omap_hwmod omap44xx_sl2if_hwmod = {
},
};
/*
* 'timer' class
* general purpose timer module with accurate 1ms tick
* This class contains several variants: ['timer_1ms', 'timer']
*/
static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
.name = "timer",
.sysc = &omap44xx_timer_1ms_sysc,
};
/* timer1 */
static struct omap_hwmod omap44xx_timer1_hwmod = {
.name = "timer1",
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.main_clk = "dmt1_clk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'usb_host_fs' class
* full-speed usb host controller
@ -1063,14 +991,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_counter_32k_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> ctrl_module_core */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
.master = &omap44xx_l4_cfg_hwmod,
@ -1199,14 +1119,6 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_timer1_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> usb_host_fs */
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
.master = &omap44xx_l4_cfg_hwmod,
@ -1273,7 +1185,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_cfg__l4_wkup,
&omap44xx_mpu__mpu_private,
&omap44xx_l4_cfg__ocp_wp_noc,
&omap44xx_l4_wkup__counter_32k,
&omap44xx_l4_cfg__ctrl_module_core,
&omap44xx_l4_cfg__ctrl_module_pad_core,
&omap44xx_l4_wkup__ctrl_module_wkup,
@ -1290,7 +1201,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_wkup__prm,
&omap44xx_l4_wkup__scrm,
/* &omap44xx_l3_main_2__sl2if, */
&omap44xx_l4_wkup__timer1,
/* &omap44xx_l4_cfg__usb_host_fs, */
&omap44xx_l4_cfg__usb_host_hs,
&omap44xx_l4_cfg__usb_tll_hs,

89
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View File

@ -193,39 +193,6 @@ static struct omap_hwmod omap54xx_mpu_private_hwmod = {
},
};
/*
* 'counter' class
* 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
*/
static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
.name = "counter",
.sysc = &omap54xx_counter_sysc,
};
/* counter_32k */
static struct omap_hwmod omap54xx_counter_32k_hwmod = {
.name = "counter_32k",
.class = &omap54xx_counter_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "wkupaon_iclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
},
},
};
/*
* 'emif' class
* external memory interface no1 (wrapper)
@ -299,44 +266,6 @@ static struct omap_hwmod omap54xx_mpu_hwmod = {
},
};
/*
* 'timer' class
* general purpose timer module with accurate 1ms tick
* This class contains several variants: ['timer_1ms', 'timer']
*/
static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
.name = "timer",
.sysc = &omap54xx_timer_1ms_sysc,
};
/* timer1 */
static struct omap_hwmod omap54xx_timer1_hwmod = {
.name = "timer1",
.class = &omap54xx_timer_1ms_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.main_clk = "timer1_gfclk_mux",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'usb_host_hs' class
* high-speed multi-port usb host controller
@ -666,14 +595,6 @@ static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
.master = &omap54xx_l4_wkup_hwmod,
.slave = &omap54xx_counter_32k_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* mpu -> emif1 */
static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
.master = &omap54xx_mpu_hwmod,
@ -698,14 +619,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
.master = &omap54xx_l4_wkup_hwmod,
.slave = &omap54xx_timer1_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> usb_host_hs */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
.master = &omap54xx_l4_cfg_hwmod,
@ -747,11 +660,9 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l3_main_2__l4_per,
&omap54xx_l3_main_1__l4_wkup,
&omap54xx_mpu__mpu_private,
&omap54xx_l4_wkup__counter_32k,
&omap54xx_mpu__emif1,
&omap54xx_mpu__emif2,
&omap54xx_l4_cfg__mpu,
&omap54xx_l4_wkup__timer1,
&omap54xx_l4_cfg__usb_host_hs,
&omap54xx_l4_cfg__usb_tll_hs,
&omap54xx_l4_cfg__usb_otg_ss,

176
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -221,40 +221,6 @@ static struct omap_hwmod dra7xx_bb2d_hwmod = {
},
};
/*
* 'counter' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
.name = "counter",
.sysc = &dra7xx_counter_sysc,
};
/* counter_32k */
static struct omap_hwmod dra7xx_counter_32k_hwmod = {
.name = "counter_32k",
.class = &dra7xx_counter_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "wkupaon_iclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
},
},
};
/*
* 'ctrl_module' class
*
@ -525,103 +491,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
},
};
/*
* 'timer' class
*
* This class contains several variants: ['timer_1ms', 'timer_secure',
* 'timer']
*/
static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
.name = "timer",
.sysc = &dra7xx_timer_1ms_sysc,
};
static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
.name = "timer",
.sysc = &dra7xx_timer_sysc,
};
/* timer1 */
static struct omap_hwmod dra7xx_timer1_hwmod = {
.name = "timer1",
.class = &dra7xx_timer_1ms_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.main_clk = "timer1_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer2 */
static struct omap_hwmod dra7xx_timer2_hwmod = {
.name = "timer2",
.class = &dra7xx_timer_1ms_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "timer2_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer3 */
static struct omap_hwmod dra7xx_timer3_hwmod = {
.name = "timer3",
.class = &dra7xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "timer3_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* timer4 */
static struct omap_hwmod dra7xx_timer4_hwmod = {
.name = "timer4",
.class = &dra7xx_timer_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "timer4_gfclk_mux",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'usb_otg_ss' class
*
@ -864,14 +733,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
.master = &dra7xx_l4_wkup_hwmod,
.slave = &dra7xx_counter_32k_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> ctrl_module_wkup */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
.master = &dra7xx_l4_wkup_hwmod,
@ -952,38 +813,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
.master = &dra7xx_l4_wkup_hwmod,
.slave = &dra7xx_timer1_hwmod,
.clk = "wkupaon_iclk_mux",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> timer2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_timer2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> timer3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_timer3_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> timer4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_timer4_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per3 -> usb_otg_ss1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
.master = &dra7xx_l4_per3_hwmod,
@ -1062,7 +891,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__l4_wkup,
&dra7xx_l4_per2__atl,
&dra7xx_l3_main_1__bb2d,
&dra7xx_l4_wkup__counter_32k,
&dra7xx_l4_wkup__ctrl_module_wkup,
&dra7xx_l3_main_1__gpmc,
&dra7xx_l4_cfg__mpu,
@ -1072,10 +900,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_cfg__pciess2,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_wkup__timer1,
&dra7xx_l4_per1__timer2,
&dra7xx_l4_per1__timer3,
&dra7xx_l4_per1__timer4,
&dra7xx_l4_per3__usb_otg_ss1,
&dra7xx_l4_per3__usb_otg_ss2,
&dra7xx_l4_per3__usb_otg_ss3,

74
arch/arm/mach-omap2/omap_hwmod_81xx_data.c
View File

@ -690,76 +690,6 @@ static struct omap_hwmod_class dm816x_timer_hwmod_class = {
.sysc = &dm816x_timer_sysc,
};
static struct omap_hwmod dm814x_timer1_hwmod = {
.name = "timer1",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer1_fck",
.class = &dm816x_timer_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm814x_timer1_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm816x_timer1_hwmod = {
.name = "timer1",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer1_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
.class = &dm816x_timer_hwmod_class,
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm816x_timer1_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm814x_timer2_hwmod = {
.name = "timer2",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer2_fck",
.class = &dm816x_timer_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm814x_timer2_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm816x_timer2_hwmod = {
.name = "timer2",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer2_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
.class = &dm816x_timer_hwmod_class,
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm816x_timer2_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm816x_timer3_hwmod = {
.name = "timer3",
.clkdm_name = "alwon_l3s_clkdm",
@ -1288,8 +1218,6 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
&dm814x_l4_ls__mmc1,
&dm814x_l4_ls__mmc2,
&ti81xx_l4_ls__rtc,
&dm814x_l4_ls__timer1,
&dm814x_l4_ls__timer2,
&dm81xx_alwon_l3_slow__gpmc,
&dm814x_default_l3_slow__usbss,
&dm814x_alwon_l3_med__mmc3,
@ -1318,8 +1246,6 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_l4_ls__elm,
&ti81xx_l4_ls__rtc,
&dm816x_l4_ls__mmc1,
&dm816x_l4_ls__timer1,
&dm816x_l4_ls__timer2,
&dm816x_l4_ls__timer3,
&dm816x_l4_ls__timer4,
&dm816x_l4_ls__timer5,

3
arch/arm/mach-omap2/omap_hwmod_common_data.h
View File

@ -21,8 +21,6 @@ extern struct omap_hwmod omap2xxx_l4_core_hwmod;
extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
extern struct omap_hwmod omap2xxx_mpu_hwmod;
extern struct omap_hwmod omap2xxx_iva_hwmod;
extern struct omap_hwmod omap2xxx_timer1_hwmod;
extern struct omap_hwmod omap2xxx_timer2_hwmod;
extern struct omap_hwmod omap2xxx_timer3_hwmod;
extern struct omap_hwmod omap2xxx_timer4_hwmod;
extern struct omap_hwmod omap2xxx_timer5_hwmod;
@ -47,7 +45,6 @@ extern struct omap_hwmod omap2xxx_gpio3_hwmod;
extern struct omap_hwmod omap2xxx_gpio4_hwmod;
extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
extern struct omap_hwmod omap2xxx_gpmc_hwmod;
extern struct omap_hwmod omap2xxx_rng_hwmod;
extern struct omap_hwmod omap2xxx_sham_hwmod;

2
arch/arm/mach-omap2/pm33xx-core.c
View File

@ -267,7 +267,7 @@ static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void)
return NULL;
}
void __iomem *am43xx_get_rtc_base_addr(void)
static void __iomem *am43xx_get_rtc_base_addr(void)
{
rtc_oh = omap_hwmod_lookup("rtc");

2
arch/arm/mach-omap2/sleep34xx.S
View File

@ -72,7 +72,7 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
stmfd sp!, {lr} @ save registers on stack
/* Setup so that we will disable and enable l2 */
mov r1, #0x1
adrl r3, l2dis_3630_offset @ may be too distant for plain adr
adr r3, l2dis_3630_offset
ldr r2, [r3] @ value for offset
str r1, [r2, r3] @ write to l2dis_3630
ldmfd sp!, {pc} @ restore regs and return

577
arch/arm/mach-omap2/timer.c
View File

@ -26,34 +26,12 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
#include <linux/sched_clock.h>
#include <asm/mach/time.h>
#include "omap_hwmod.h"
#include "omap_device.h"
#include <plat/counter-32k.h>
#include <clocksource/timer-ti-dm.h>
#include "soc.h"
#include "common.h"
#include "control.h"
#include "powerdomain.h"
#include "omap-secure.h"
#define REALTIME_COUNTER_BASE 0x48243200
@ -61,537 +39,12 @@
#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
/* Clockevent code */
static struct omap_dm_timer clkev;
static struct clock_event_device clockevent_gpt;
/* Clockevent hwmod for am335x and am437x suspend */
static struct omap_hwmod *clockevent_gpt_hwmod;
/* Clockesource hwmod for am437x suspend */
static struct omap_hwmod *clocksource_gpt_hwmod;
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
static unsigned long arch_timer_freq;
void set_cntfreq(void)
{
omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
}
#endif
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &clockevent_gpt;
__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static int omap2_gp_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
0xffffffff - cycles, OMAP_TIMER_POSTED);
return 0;
}
static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
{
__omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
return 0;
}
static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
{
u32 period;
__omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
period = clkev.rate / HZ;
period -= 1;
/* Looks like we need to first set the load value separately */
__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
OMAP_TIMER_POSTED);
__omap_dm_timer_load_start(&clkev,
OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
0xffffffff - period, OMAP_TIMER_POSTED);
return 0;
}
static void omap_clkevt_idle(struct clock_event_device *unused)
{
if (!clockevent_gpt_hwmod)
return;
omap_hwmod_idle(clockevent_gpt_hwmod);
}
static void omap_clkevt_unidle(struct clock_event_device *unused)
{
if (!clockevent_gpt_hwmod)
return;
omap_hwmod_enable(clockevent_gpt_hwmod);
__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
}
static struct clock_event_device clockevent_gpt = {
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.rating = 300,
.set_next_event = omap2_gp_timer_set_next_event,
.set_state_shutdown = omap2_gp_timer_shutdown,
.set_state_periodic = omap2_gp_timer_set_periodic,
.set_state_oneshot = omap2_gp_timer_shutdown,
.tick_resume = omap2_gp_timer_shutdown,
};
static const struct of_device_id omap_timer_match[] __initconst = {
{ .compatible = "ti,omap2420-timer", },
{ .compatible = "ti,omap3430-timer", },
{ .compatible = "ti,omap4430-timer", },
{ .compatible = "ti,omap5430-timer", },
{ .compatible = "ti,dm814-timer", },
{ .compatible = "ti,dm816-timer", },
{ .compatible = "ti,am335x-timer", },
{ .compatible = "ti,am335x-timer-1ms", },
{ }
};
static int omap_timer_add_disabled_property(struct device_node *np)
{
struct property *prop;
prop = kzalloc(sizeof(*prop), GFP_KERNEL);
if (!prop)
return -ENOMEM;
prop->name = "status";
prop->value = "disabled";
prop->length = strlen(prop->value);
return of_add_property(np, prop);
}
static int omap_timer_update_dt(struct device_node *np)
{
int error = 0;
if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
error = omap_timer_add_disabled_property(np);
if (error)
return error;
}
/* No parent interconnect target module configured? */
if (of_get_property(np, "ti,hwmods", NULL))
return error;
/* Tag parent interconnect target module disabled */
error = omap_timer_add_disabled_property(np->parent);
if (error)
return error;
return 0;
}
/**
* omap_get_timer_dt - get a timer using device-tree
* @match - device-tree match structure for matching a device type
* @property - optional timer property to match
*
* Helper function to get a timer during early boot using device-tree for use
* as kernel system timer. Optionally, the property argument can be used to
* select a timer with a specific property. Once a timer is found then mark
* the timer node in device-tree as disabled, to prevent the kernel from
* registering this timer as a platform device and so no one else can use it.
*/
static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
const char *property)
{
struct device_node *np;
int error;
for_each_matching_node(np, match) {
if (!of_device_is_available(np))
continue;
if (property && !of_get_property(np, property, NULL))
continue;
if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
of_get_property(np, "ti,timer-dsp", NULL) ||
of_get_property(np, "ti,timer-pwm", NULL) ||
of_get_property(np, "ti,timer-secure", NULL)))
continue;
error = omap_timer_update_dt(np);
WARN(error, "%s: Could not update dt: %i\n", __func__, error);
return np;
}
return NULL;
}
/**
* omap_dmtimer_init - initialisation function when device tree is used
*
* For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
* cannot be used by the kernel as they are reserved. Therefore, to prevent the
* kernel registering these devices remove them dynamically from the device
* tree on boot.
*/
static void __init omap_dmtimer_init(void)
{
struct device_node *np;
if (!cpu_is_omap34xx() && !soc_is_dra7xx())
return;
/* If we are a secure device, remove any secure timer nodes */
if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
of_node_put(np);
}
}
/**
* omap_dm_timer_get_errata - get errata flags for a timer
*
* Get the timer errata flags that are specific to the OMAP device being used.
*/
static u32 __init omap_dm_timer_get_errata(void)
{
if (cpu_is_omap24xx())
return 0;
return OMAP_TIMER_ERRATA_I103_I767;
}
static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
const char *fck_source,
const char *property,
const char **timer_name,
int posted)
{
const char *oh_name = NULL;
struct device_node *np;
struct omap_hwmod *oh;
struct clk *src;
int r = 0;
np = omap_get_timer_dt(omap_timer_match, property);
if (!np)
return -ENODEV;
of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
if (!oh_name) {
of_property_read_string_index(np->parent, "ti,hwmods", 0,
&oh_name);
if (!oh_name)
return -ENODEV;
}
timer->irq = irq_of_parse_and_map(np, 0);
if (!timer->irq)
return -ENXIO;
timer->io_base = of_iomap(np, 0);
timer->fclk = of_clk_get_by_name(np, "fck");
of_node_put(np);
oh = omap_hwmod_lookup(oh_name);
if (!oh)
return -ENODEV;
*timer_name = oh->name;
if (!timer->io_base)
return -ENXIO;
omap_hwmod_setup_one(oh_name);
/* After the dmtimer is using hwmod these clocks won't be needed */
if (IS_ERR_OR_NULL(timer->fclk))
timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
if (IS_ERR(timer->fclk))
return PTR_ERR(timer->fclk);
src = clk_get(NULL, fck_source);
if (IS_ERR(src))
return PTR_ERR(src);
WARN(clk_set_parent(timer->fclk, src) < 0,
"Cannot set timer parent clock, no PLL clock driver?");
clk_put(src);
omap_hwmod_enable(oh);
__omap_dm_timer_init_regs(timer);
if (posted)
__omap_dm_timer_enable_posted(timer);
/* Check that the intended posted configuration matches the actual */
if (posted != timer->posted)
return -EINVAL;
timer->rate = clk_get_rate(timer->fclk);
timer->reserved = 1;
return r;
}
#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
void tick_broadcast(const struct cpumask *mask)
{
}
#endif
static void __init omap2_gp_clockevent_init(int gptimer_id,
const char *fck_source,
const char *property)
{
int res;
clkev.id = gptimer_id;
clkev.errata = omap_dm_timer_get_errata();
/*
* For clock-event timers we never read the timer counter and
* so we are not impacted by errata i103 and i767. Therefore,
* we can safely ignore this errata for clock-event timers.
*/
__omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
res = omap_dm_timer_init_one(&clkev, fck_source, property,
&clockevent_gpt.name, OMAP_TIMER_POSTED);
BUG_ON(res);
if (request_irq(clkev.irq, omap2_gp_timer_interrupt,
IRQF_TIMER | IRQF_IRQPOLL, "gp_timer", &clkev))
pr_err("Failed to request irq %d (gp_timer)\n", clkev.irq);
__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
clockevent_gpt.cpumask = cpu_possible_mask;
clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
clockevents_config_and_register(&clockevent_gpt, clkev.rate,
3, /* Timer internal resynch latency */
0xffffffff);
if (soc_is_am33xx() || soc_is_am43xx()) {
clockevent_gpt.suspend = omap_clkevt_idle;
clockevent_gpt.resume = omap_clkevt_unidle;
clockevent_gpt_hwmod =
omap_hwmod_lookup(clockevent_gpt.name);
}
pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
clkev.rate);
}
/* Clocksource code */
static struct omap_dm_timer clksrc;
static bool use_gptimer_clksrc __initdata;
/*
* clocksource
*/
static u64 clocksource_read_cycles(struct clocksource *cs)
{
return (u64)__omap_dm_timer_read_counter(&clksrc,
OMAP_TIMER_NONPOSTED);
}
static struct clocksource clocksource_gpt = {
.rating = 300,
.read = clocksource_read_cycles,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static u64 notrace dmtimer_read_sched_clock(void)
{
if (clksrc.reserved)
return __omap_dm_timer_read_counter(&clksrc,
OMAP_TIMER_NONPOSTED);
return 0;
}
static const struct of_device_id omap_counter_match[] __initconst = {
{ .compatible = "ti,omap-counter32k", },
{ }
};
/* Setup free-running counter for clocksource */
static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
{
int ret;
struct device_node *np = NULL;
struct omap_hwmod *oh;
const char *oh_name = "counter_32k";
/*
* See if the 32kHz counter is supported.
*/
np = omap_get_timer_dt(omap_counter_match, NULL);
if (!np)
return -ENODEV;
of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name);
if (!oh_name) {
of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
if (!oh_name)
return -ENODEV;
}
/*
* First check hwmod data is available for sync32k counter
*/
oh = omap_hwmod_lookup(oh_name);
if (!oh || oh->slaves_cnt == 0)
return -ENODEV;
omap_hwmod_setup_one(oh_name);
ret = omap_hwmod_enable(oh);
if (ret) {
pr_warn("%s: failed to enable counter_32k module (%d)\n",
__func__, ret);
return ret;
}
return ret;
}
static unsigned int omap2_gptimer_clksrc_load;
static void omap2_gptimer_clksrc_suspend(struct clocksource *unused)
{
omap2_gptimer_clksrc_load =
__omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
omap_hwmod_idle(clocksource_gpt_hwmod);
}
static void omap2_gptimer_clksrc_resume(struct clocksource *unused)
{
omap_hwmod_enable(clocksource_gpt_hwmod);
__omap_dm_timer_load_start(&clksrc,
OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
omap2_gptimer_clksrc_load,
OMAP_TIMER_NONPOSTED);
}
static void __init omap2_gptimer_clocksource_init(int gptimer_id,
const char *fck_source,
const char *property)
{
int res;
clksrc.id = gptimer_id;
clksrc.errata = omap_dm_timer_get_errata();
res = omap_dm_timer_init_one(&clksrc, fck_source, property,
&clocksource_gpt.name,
OMAP_TIMER_NONPOSTED);
if (soc_is_am43xx()) {
clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend;
clocksource_gpt.resume = omap2_gptimer_clksrc_resume;
clocksource_gpt_hwmod =
omap_hwmod_lookup(clocksource_gpt.name);
}
BUG_ON(res);
__omap_dm_timer_load_start(&clksrc,
OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
OMAP_TIMER_NONPOSTED);
sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
pr_err("Could not register clocksource %s\n",
clocksource_gpt.name);
else
pr_info("OMAP clocksource: %s at %lu Hz\n",
clocksource_gpt.name, clksrc.rate);
}
static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
const char *clksrc_prop, bool gptimer)
{
omap_clk_init();
omap_dmtimer_init();
omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
/* Enable the use of clocksource="gp_timer" kernel parameter */
if (clksrc_nr && (use_gptimer_clksrc || gptimer))
omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
clksrc_prop);
else
omap2_sync32k_clocksource_init();
}
void __init omap_init_time(void)
{
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
2, "timer_sys_ck", NULL, false);
timer_probe();
}
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
void __init omap3_secure_sync32k_timer_init(void)
{
__omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
2, "timer_sys_ck", NULL, false);
timer_probe();
}
#endif /* CONFIG_ARCH_OMAP3 */
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
defined(CONFIG_SOC_AM43XX)
void __init omap3_gptimer_timer_init(void)
{
__omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
1, "timer_sys_ck", "ti,timer-alwon", true);
if (of_have_populated_dt())
timer_probe();
}
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX)
static void __init omap4_sync32k_timer_init(void)
{
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
0, NULL, NULL, false);
}
void __init omap4_local_timer_init(void)
{
omap4_sync32k_timer_init();
timer_probe();
}
#endif
#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
/*
* The realtime counter also called master counter, is a free-running
@ -604,7 +57,6 @@ void __init omap4_local_timer_init(void)
*/
static void __init realtime_counter_init(void)
{
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
void __iomem *base;
static struct clk *sys_clk;
unsigned long rate;
@ -703,39 +155,12 @@ sysclk1_based:
set_cntfreq();
iounmap(base);
#endif
}
void __init omap5_realtime_timer_init(void)
{
omap4_sync32k_timer_init();
omap_clk_init();
realtime_counter_init();
timer_probe();
}
#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
/**
* omap2_override_clocksource - clocksource override with user configuration
*
* Allows user to override default clocksource, using kernel parameter
* clocksource="gp_timer" (For all OMAP2PLUS architectures)
*
* Note that, here we are using same standard kernel parameter "clocksource=",
* and not introducing any OMAP specific interface.
*/
static int __init omap2_override_clocksource(char *str)
{
if (!str)
return 0;
/*
* For OMAP architecture, we only have two options
* - sync_32k (default)
* - gp_timer (sys_clk based)
*/
if (!strcmp(str, "gp_timer"))
use_gptimer_clksrc = true;
return 0;
}
early_param("clocksource", omap2_override_clocksource);

1
arch/arm/mach-prima2/Kconfig
View File

@ -30,7 +30,6 @@ config ARCH_ATLAS7
select ARM_GIC
select ATLAS7_TIMER
select HAVE_ARM_SCU if SMP
select HAVE_SMP
help
Support for CSR SiRFSoC ARM Cortex A7 Platform

17
arch/arm/mach-pxa/Kconfig
View File

@ -123,23 +123,6 @@ config CSB726_CSB701
bool "Enable support for CSB701 baseboard"
depends on MACH_CSB726
config MACH_ARMCORE
bool "CompuLab CM-X255/CM-X270 modules"
select ARCH_HAS_DMA_SET_COHERENT_MASK if PCI
select IWMMXT
select HAVE_PCI
select NEED_MACH_IO_H if PCI
select PXA25x
select PXA27x
config MACH_EM_X270
bool "CompuLab EM-x270 platform"
select PXA27x
config MACH_EXEDA
bool "CompuLab eXeda platform"
select PXA27x
config MACH_CM_X300
bool "CompuLab CM-X300 modules"
select CPU_PXA300

5
arch/arm/mach-pxa/Makefile
View File

@ -40,11 +40,6 @@ obj-$(CONFIG_MACH_ARCOM_ZEUS) += zeus.o
obj-$(CONFIG_MACH_BALLOON3) += balloon3.o
obj-$(CONFIG_MACH_CSB726) += csb726.o
obj-$(CONFIG_CSB726_CSB701) += csb701.o
obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o
ifeq ($(CONFIG_PCI),y)
obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o
endif
obj-$(CONFIG_MACH_EM_X270) += em-x270.o
obj-$(CONFIG_MACH_CM_X300) += cm-x300.o
obj-$(CONFIG_MACH_CAPC7117) += capc7117.o mxm8x10.o
obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o

240
arch/arm/mach-pxa/cm-x255.c
View File

@ -1,240 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-pxa/cm-x255.c
*
* Copyright (C) 2007, 2008 CompuLab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
*/
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand-gpio.h>
#include <linux/gpio/machine.h>
#include <linux/spi/spi.h>
#include <linux/spi/pxa2xx_spi.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include "pxa25x.h"
#include "generic.h"
#define GPIO_NAND_CS (5)
#define GPIO_NAND_ALE (4)
#define GPIO_NAND_CLE (3)
#define GPIO_NAND_RB (10)
static unsigned long cmx255_pin_config[] = {
/* AC'97 */
GPIO28_AC97_BITCLK,
GPIO29_AC97_SDATA_IN_0,
GPIO30_AC97_SDATA_OUT,
GPIO31_AC97_SYNC,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_BTUART_RTS,
/* STUART */
GPIO46_STUART_RXD,
GPIO47_STUART_TXD,
/* LCD */
GPIOxx_LCD_TFT_16BPP,
/* SSP1 */
GPIO23_SSP1_SCLK,
GPIO24_SSP1_SFRM,
GPIO25_SSP1_TXD,
GPIO26_SSP1_RXD,
/* SSP2 */
GPIO81_SSP2_CLK_OUT,
GPIO82_SSP2_FRM_OUT,
GPIO83_SSP2_TXD,
GPIO84_SSP2_RXD,
/* PC Card */
GPIO48_nPOE,
GPIO49_nPWE,
GPIO50_nPIOR,
GPIO51_nPIOW,
GPIO52_nPCE_1,
GPIO53_nPCE_2,
GPIO54_nPSKTSEL,
GPIO55_nPREG,
GPIO56_nPWAIT,
GPIO57_nIOIS16,
/* SDRAM and local bus */
GPIO15_nCS_1,
GPIO78_nCS_2,
GPIO79_nCS_3,
GPIO80_nCS_4,
GPIO33_nCS_5,
GPIO18_RDY,
/* GPIO */
GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,
GPIO9_GPIO, /* PC card reset */
/* NAND controls */
GPIO5_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
GPIO4_GPIO | MFP_LPM_DRIVE_LOW, /* NAND ALE */
GPIO3_GPIO | MFP_LPM_DRIVE_LOW, /* NAND CLE */
GPIO10_GPIO, /* NAND Ready/Busy */
/* interrupts */
GPIO22_GPIO, /* DM9000 interrupt */
};
#if defined(CONFIG_SPI_PXA2XX)
static struct pxa2xx_spi_controller pxa_ssp_master_info = {
.num_chipselect = 1,
};
static struct spi_board_info spi_board_info[] __initdata = {
[0] = {
.modalias = "rtc-max6902",
.max_speed_hz = 1000000,
.bus_num = 1,
.chip_select = 0,
},
};
static void __init cmx255_init_rtc(void)
{
pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
spi_register_board_info(ARRAY_AND_SIZE(spi_board_info));
}
#else
static inline void cmx255_init_rtc(void) {}
#endif
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static struct mtd_partition cmx255_nor_partitions[] = {
{
.name = "ARMmon",
.size = 0x00030000,
.offset = 0,
.mask_flags = MTD_WRITEABLE /* force read-only */
} , {
.name = "ARMmon setup block",
.size = 0x00010000,
.offset = MTDPART_OFS_APPEND,
.mask_flags = MTD_WRITEABLE /* force read-only */
} , {
.name = "kernel",
.size = 0x00160000,
.offset = MTDPART_OFS_APPEND,
} , {
.name = "ramdisk",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND
}
};
static struct physmap_flash_data cmx255_nor_flash_data[] = {
{
.width = 2, /* bankwidth in bytes */
.parts = cmx255_nor_partitions,
.nr_parts = ARRAY_SIZE(cmx255_nor_partitions)
}
};
static struct resource cmx255_nor_resource = {
.start = PXA_CS0_PHYS,
.end = PXA_CS0_PHYS + SZ_8M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device cmx255_nor = {
.name = "physmap-flash",
.id = -1,
.dev = {
.platform_data = cmx255_nor_flash_data,
},
.resource = &cmx255_nor_resource,
.num_resources = 1,
};
static void __init cmx255_init_nor(void)
{
platform_device_register(&cmx255_nor);
}
#else
static inline void cmx255_init_nor(void) {}
#endif
#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
static struct gpiod_lookup_table cmx255_nand_gpiod_table = {
.dev_id = "gpio-nand",
.table = {
GPIO_LOOKUP("gpio-pxa", GPIO_NAND_CS, "nce", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("gpio-pxa", GPIO_NAND_CLE, "cle", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("gpio-pxa", GPIO_NAND_ALE, "ale", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("gpio-pxa", GPIO_NAND_RB, "rdy", GPIO_ACTIVE_HIGH),
},
};
static struct resource cmx255_nand_resource[] = {
[0] = {
.start = PXA_CS1_PHYS,
.end = PXA_CS1_PHYS + 11,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PXA_CS5_PHYS,
.end = PXA_CS5_PHYS + 3,
.flags = IORESOURCE_MEM,
},
};
static struct mtd_partition cmx255_nand_parts[] = {
[0] = {
.name = "cmx255-nand",
.size = MTDPART_SIZ_FULL,
.offset = 0,
},
};
static struct gpio_nand_platdata cmx255_nand_platdata = {
.parts = cmx255_nand_parts,
.num_parts = ARRAY_SIZE(cmx255_nand_parts),
.chip_delay = 25,
};
static struct platform_device cmx255_nand = {
.name = "gpio-nand",
.num_resources = ARRAY_SIZE(cmx255_nand_resource),
.resource = cmx255_nand_resource,
.id = -1,
.dev = {
.platform_data = &cmx255_nand_platdata,
}
};
static void __init cmx255_init_nand(void)
{
gpiod_add_lookup_table(&cmx255_nand_gpiod_table);
platform_device_register(&cmx255_nand);
}
#else
static inline void cmx255_init_nand(void) {}
#endif
void __init cmx255_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config));
cmx255_init_rtc();
cmx255_init_nor();
cmx255_init_nand();
}

419
arch/arm/mach-pxa/cm-x270.c
View File

@ -1,419 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-pxa/cm-x270.c
*
* Copyright (C) 2007, 2008 CompuLab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
*/
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/delay.h>
#include <linux/platform_data/rtc-v3020.h>
#include <video/mbxfb.h>
#include <linux/spi/spi.h>
#include <linux/spi/pxa2xx_spi.h>
#include <linux/spi/libertas_spi.h>
#include "pxa27x.h"
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include <linux/platform_data/mmc-pxamci.h>
#include "generic.h"
/* physical address if local-bus attached devices */
#define RTC_PHYS_BASE (PXA_CS1_PHYS + (5 << 22))
/* GPIO IRQ usage */
#define GPIO83_MMC_IRQ (83)
#define CMX270_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO83_MMC_IRQ)
/* MMC power enable */
#define GPIO105_MMC_POWER (105)
/* WLAN GPIOS */
#define GPIO19_WLAN_STRAP (19)
#define GPIO102_WLAN_RST (102)
static unsigned long cmx270_pin_config[] = {
/* AC'97 */
GPIO28_AC97_BITCLK,
GPIO29_AC97_SDATA_IN_0,
GPIO30_AC97_SDATA_OUT,
GPIO31_AC97_SYNC,
GPIO98_AC97_SYSCLK,
GPIO113_AC97_nRESET,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_BTUART_RTS,
/* STUART */
GPIO46_STUART_RXD,
GPIO47_STUART_TXD,
/* MCI controller */
GPIO32_MMC_CLK,
GPIO112_MMC_CMD,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
/* LCD */
GPIOxx_LCD_TFT_16BPP,
/* I2C */
GPIO117_I2C_SCL,
GPIO118_I2C_SDA,
/* SSP1 */
GPIO23_SSP1_SCLK,
GPIO24_SSP1_SFRM,
GPIO25_SSP1_TXD,
GPIO26_SSP1_RXD,
/* SSP2 */
GPIO19_GPIO, /* SSP2 clock is used as GPIO for Libertas pin-strap */
GPIO14_GPIO,
GPIO87_SSP2_TXD,
GPIO88_SSP2_RXD,
/* PC Card */
GPIO48_nPOE,
GPIO49_nPWE,
GPIO50_nPIOR,
GPIO51_nPIOW,
GPIO85_nPCE_1,
GPIO54_nPCE_2,
GPIO55_nPREG,
GPIO56_nPWAIT,
GPIO57_nIOIS16,
/* SDRAM and local bus */
GPIO15_nCS_1,
GPIO78_nCS_2,
GPIO79_nCS_3,
GPIO80_nCS_4,
GPIO33_nCS_5,
GPIO49_nPWE,
GPIO18_RDY,
/* GPIO */
GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,
GPIO105_GPIO | MFP_LPM_DRIVE_HIGH, /* MMC/SD power */
GPIO53_GPIO, /* PC card reset */
GPIO102_GPIO, /* WLAN reset */
/* NAND controls */
GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
GPIO89_GPIO, /* NAND Ready/Busy */
/* interrupts */
GPIO10_GPIO, /* DM9000 interrupt */
GPIO83_GPIO, /* MMC card detect */
GPIO95_GPIO, /* WLAN interrupt */
};
/* V3020 RTC */
#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
static struct resource cmx270_v3020_resource[] = {
[0] = {
.start = RTC_PHYS_BASE,
.end = RTC_PHYS_BASE + 4,
.flags = IORESOURCE_MEM,
},
};
struct v3020_platform_data cmx270_v3020_pdata = {
.leftshift = 16,
};
static struct platform_device cmx270_rtc_device = {
.name = "v3020",
.num_resources = ARRAY_SIZE(cmx270_v3020_resource),
.resource = cmx270_v3020_resource,
.id = -1,
.dev = {
.platform_data = &cmx270_v3020_pdata,
}
};
static void __init cmx270_init_rtc(void)
{
platform_device_register(&cmx270_rtc_device);
}
#else
static inline void cmx270_init_rtc(void) {}
#endif
/* 2700G graphics */
#if defined(CONFIG_FB_MBX) || defined(CONFIG_FB_MBX_MODULE)
static u64 fb_dma_mask = ~(u64)0;
static struct resource cmx270_2700G_resource[] = {
/* frame buffer memory including ODFB and External SDRAM */
[0] = {
.start = PXA_CS2_PHYS,
.end = PXA_CS2_PHYS + 0x01ffffff,
.flags = IORESOURCE_MEM,
},
/* Marathon registers */
[1] = {
.start = PXA_CS2_PHYS + 0x03fe0000,
.end = PXA_CS2_PHYS + 0x03ffffff,
.flags = IORESOURCE_MEM,
},
};
static unsigned long cmx270_marathon_on[] = {
GPIO58_GPIO,
GPIO59_GPIO,
GPIO60_GPIO,
GPIO61_GPIO,
GPIO62_GPIO,
GPIO63_GPIO,
GPIO64_GPIO,
GPIO65_GPIO,
GPIO66_GPIO,
GPIO67_GPIO,
GPIO68_GPIO,
GPIO69_GPIO,
GPIO70_GPIO,
GPIO71_GPIO,
GPIO72_GPIO,
GPIO73_GPIO,
GPIO74_GPIO,
GPIO75_GPIO,
GPIO76_GPIO,
GPIO77_GPIO,
};
static unsigned long cmx270_marathon_off[] = {
GPIOxx_LCD_TFT_16BPP,
};
static int cmx270_marathon_probe(struct fb_info *fb)
{
int gpio, err;
for (gpio = 58; gpio <= 77; gpio++) {
err = gpio_request(gpio, "LCD");
if (err)
return err;
gpio_direction_input(gpio);
}
pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_marathon_on));
return 0;
}
static int cmx270_marathon_remove(struct fb_info *fb)
{
int gpio;
pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_marathon_off));
for (gpio = 58; gpio <= 77; gpio++)
gpio_free(gpio);
return 0;
}
static struct mbxfb_platform_data cmx270_2700G_data = {
.xres = {
.min = 240,
.max = 1200,
.defval = 640,
},
.yres = {
.min = 240,
.max = 1200,
.defval = 480,
},
.bpp = {
.min = 16,
.max = 32,
.defval = 16,
},
.memsize = 8*1024*1024,
.probe = cmx270_marathon_probe,
.remove = cmx270_marathon_remove,
};
static struct platform_device cmx270_2700G = {
.name = "mbx-fb",
.dev = {
.platform_data = &cmx270_2700G_data,
.dma_mask = &fb_dma_mask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(cmx270_2700G_resource),
.resource = cmx270_2700G_resource,
.id = -1,
};
static void __init cmx270_init_2700G(void)
{
platform_device_register(&cmx270_2700G);
}
#else
static inline void cmx270_init_2700G(void) {}
#endif
/* PXA27x OHCI controller setup */
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static struct pxaohci_platform_data cmx270_ohci_platform_data = {
.port_mode = PMM_PERPORT_MODE,
.flags = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
};
static void __init cmx270_init_ohci(void)
{
pxa_set_ohci_info(&cmx270_ohci_platform_data);
}
#else
static inline void cmx270_init_ohci(void) {}
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
static struct pxamci_platform_data cmx270_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
};
static struct gpiod_lookup_table cmx270_mci_gpio_table = {
.dev_id = "pxa2xx-mci.0",
.table = {
/* Card detect on GPIO 83 */
GPIO_LOOKUP("gpio-pxa", GPIO83_MMC_IRQ, "cd", GPIO_ACTIVE_LOW),
/* Power on GPIO 105 */
GPIO_LOOKUP("gpio-pxa", GPIO105_MMC_POWER,
"power", GPIO_ACTIVE_LOW),
{ },
},
};
static void __init cmx270_init_mmc(void)
{
gpiod_add_lookup_table(&cmx270_mci_gpio_table);
pxa_set_mci_info(&cmx270_mci_platform_data);
}
#else
static inline void cmx270_init_mmc(void) {}
#endif
#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
static struct pxa2xx_spi_controller cm_x270_spi_info = {
.num_chipselect = 1,
.enable_dma = 1,
};
static struct pxa2xx_spi_chip cm_x270_libertas_chip = {
.rx_threshold = 1,
.tx_threshold = 1,
.timeout = 1000,
.gpio_cs = 14,
};
static unsigned long cm_x270_libertas_pin_config[] = {
/* SSP2 */
GPIO19_SSP2_SCLK,
GPIO14_GPIO,
GPIO87_SSP2_TXD,
GPIO88_SSP2_RXD,
};
static int cm_x270_libertas_setup(struct spi_device *spi)
{
int err = gpio_request(GPIO19_WLAN_STRAP, "WLAN STRAP");
if (err)
return err;
err = gpio_request(GPIO102_WLAN_RST, "WLAN RST");
if (err)
goto err_free_strap;
err = gpio_direction_output(GPIO102_WLAN_RST, 0);
if (err)
goto err_free_strap;
msleep(100);
err = gpio_direction_output(GPIO19_WLAN_STRAP, 1);
if (err)
goto err_free_strap;
msleep(100);
pxa2xx_mfp_config(ARRAY_AND_SIZE(cm_x270_libertas_pin_config));
gpio_set_value(GPIO102_WLAN_RST, 1);
msleep(100);
spi->bits_per_word = 16;
spi_setup(spi);
return 0;
err_free_strap:
gpio_free(GPIO19_WLAN_STRAP);
return err;
}
static int cm_x270_libertas_teardown(struct spi_device *spi)
{
gpio_set_value(GPIO102_WLAN_RST, 0);
gpio_free(GPIO102_WLAN_RST);
gpio_free(GPIO19_WLAN_STRAP);
return 0;
}
struct libertas_spi_platform_data cm_x270_libertas_pdata = {
.use_dummy_writes = 1,
.setup = cm_x270_libertas_setup,
.teardown = cm_x270_libertas_teardown,
};
static struct spi_board_info cm_x270_spi_devices[] __initdata = {
{
.modalias = "libertas_spi",
.max_speed_hz = 13000000,
.bus_num = 2,
.irq = PXA_GPIO_TO_IRQ(95),
.chip_select = 0,
.controller_data = &cm_x270_libertas_chip,
.platform_data = &cm_x270_libertas_pdata,
},
};
static void __init cmx270_init_spi(void)
{
pxa2xx_set_spi_info(2, &cm_x270_spi_info);
spi_register_board_info(ARRAY_AND_SIZE(cm_x270_spi_devices));
}
#else
static inline void cmx270_init_spi(void) {}
#endif
void __init cmx270_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_pin_config));
#ifdef CONFIG_PM
pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP);
#endif
cmx270_init_rtc();
cmx270_init_mmc();
cmx270_init_ohci();
cmx270_init_2700G();
cmx270_init_spi();
}

196
arch/arm/mach-pxa/cm-x2xx-pci.c
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@ -1,196 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-pxa/cm-x2xx-pci.c
*
* PCI bios-type initialisation for PCI machines
*
* Bits taken from various places.
*
* Copyright (C) 2007, 2008 Compulab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include <asm/hardware/it8152.h>
void __iomem *it8152_base_address;
static int cmx2xx_it8152_irq_gpio;
static void cmx2xx_it8152_irq_demux(struct irq_desc *desc)
{
/* clear our parent irq */
desc->irq_data.chip->irq_ack(&desc->irq_data);
it8152_irq_demux(desc);
}
void __cmx2xx_pci_init_irq(int irq_gpio)
{
it8152_init_irq();
cmx2xx_it8152_irq_gpio = irq_gpio;
irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
irq_set_chained_handler(gpio_to_irq(irq_gpio),
cmx2xx_it8152_irq_demux);
}
#ifdef CONFIG_PM
static unsigned long sleep_save_ite[10];
void __cmx2xx_pci_suspend(void)
{
/* save ITE state */
sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR);
sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR);
/* Clear ITE IRQ's */
__raw_writel((0), IT8152_INTC_PDCNIRR);
__raw_writel((0), IT8152_INTC_LPCNIRR);
}
void __cmx2xx_pci_resume(void)
{
/* restore IT8152 state */
__raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
__raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR);
__raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
}
#else
void cmx2xx_pci_suspend(void) {}
void cmx2xx_pci_resume(void) {}
#endif
/* PCI IRQ mapping*/
static int __init cmx2xx_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __func__, slot, pin);
irq = it8152_pci_map_irq(dev, slot, pin);
if (irq)
return irq;
/*
Here comes the ugly part. The routing is baseboard specific,
but defining a platform for each possible base of CM-X2XX is
unrealistic. Here we keep mapping for ATXBase and SB-X2XX.
*/
/* ATXBASE PCI slot */
if (slot == 7)
return IT8152_PCI_INTA;
/* ATXBase/SB-X2XX CardBus */
if (slot == 8 || slot == 0)
return IT8152_PCI_INTB;
/* ATXBase Ethernet */
if (slot == 9)
return IT8152_PCI_INTA;
/* CM-x255 Onboard Ethernet */
if (slot == 15)
return IT8152_PCI_INTC;
/* SB-x2xx Ethernet */
if (slot == 16)
return IT8152_PCI_INTA;
/* PC104+ interrupt routing */
if ((slot == 17) || (slot == 19))
return IT8152_PCI_INTA;
if ((slot == 18) || (slot == 20))
return IT8152_PCI_INTB;
return(0);
}
static void cmx2xx_pci_preinit(void)
{
pr_info("Initializing CM-X2XX PCI subsystem\n");
pcibios_min_io = 0;
pcibios_min_mem = 0;
__raw_writel(0x800, IT8152_PCI_CFG_ADDR);
if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
pr_info("PCI Bridge found.\n");
/* set PCI I/O base at 0 */
writel(0x848, IT8152_PCI_CFG_ADDR);
writel(0, IT8152_PCI_CFG_DATA);
/* set PCI memory base at 0 */
writel(0x840, IT8152_PCI_CFG_ADDR);
writel(0, IT8152_PCI_CFG_DATA);
writel(0x20, IT8152_GPIO_GPDR);
/* CardBus Controller on ATXbase baseboard */
writel(0x4000, IT8152_PCI_CFG_ADDR);
if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
pr_info("CardBus Bridge found.\n");
/* Configure socket 0 */
writel(0x408C, IT8152_PCI_CFG_ADDR);
writel(0x1022, IT8152_PCI_CFG_DATA);
writel(0x4080, IT8152_PCI_CFG_ADDR);
writel(0x3844d060, IT8152_PCI_CFG_DATA);
writel(0x4090, IT8152_PCI_CFG_ADDR);
writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
0x60440000),
IT8152_PCI_CFG_DATA);
writel(0x4018, IT8152_PCI_CFG_ADDR);
writel(0xb0000000, IT8152_PCI_CFG_DATA);
/* Configure socket 1 */
writel(0x418C, IT8152_PCI_CFG_ADDR);
writel(0x1022, IT8152_PCI_CFG_DATA);
writel(0x4180, IT8152_PCI_CFG_ADDR);
writel(0x3844d060, IT8152_PCI_CFG_DATA);
writel(0x4190, IT8152_PCI_CFG_ADDR);
writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
0x60440000),
IT8152_PCI_CFG_DATA);
writel(0x4118, IT8152_PCI_CFG_ADDR);
writel(0xb0000000, IT8152_PCI_CFG_DATA);
}
}
}
static struct hw_pci cmx2xx_pci __initdata = {
.map_irq = cmx2xx_pci_map_irq,
.nr_controllers = 1,
.ops = &it8152_ops,
.setup = it8152_pci_setup,
.preinit = cmx2xx_pci_preinit,
};
static int __init cmx2xx_init_pci(void)
{
if (machine_is_armcore())
pci_common_init(&cmx2xx_pci);
return 0;
}
subsys_initcall(cmx2xx_init_pci);

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arch/arm/mach-pxa/cm-x2xx-pci.h
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/* SPDX-License-Identifier: GPL-2.0 */
extern void __cmx2xx_pci_init_irq(int irq_gpio);
extern void __cmx2xx_pci_suspend(void);
extern void __cmx2xx_pci_resume(void);
#ifdef CONFIG_PCI
#define cmx2xx_pci_init_irq(x) __cmx2xx_pci_init_irq(x)
#define cmx2xx_pci_suspend(x) __cmx2xx_pci_suspend(x)
#define cmx2xx_pci_resume(x) __cmx2xx_pci_resume(x)
#else
#define cmx2xx_pci_init_irq(x) do {} while (0)
#define cmx2xx_pci_suspend(x) do {} while (0)
#define cmx2xx_pci_resume(x) do {} while (0)
#endif

538
arch/arm/mach-pxa/cm-x2xx.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-pxa/cm-x2xx.c
*
* Copyright (C) 2008 CompuLab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
*/
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/regulator/machine.h>
#include <linux/dm9000.h>
#include <linux/leds.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include "pxa25x.h"
#undef GPIO24_SSP1_SFRM
#undef GPIO86_GPIO
#undef GPIO87_GPIO
#undef GPIO88_GPIO
#undef GPIO89_GPIO
#include "pxa27x.h"
#undef GPIO24_SSP1_SFRM
#undef GPIO86_GPIO
#undef GPIO87_GPIO
#undef GPIO88_GPIO
#undef GPIO89_GPIO
#include <mach/audio.h>
#include <linux/platform_data/video-pxafb.h>
#include <mach/smemc.h>
#include <asm/hardware/it8152.h>
#include "generic.h"
#include "cm-x2xx-pci.h"
extern void cmx255_init(void);
extern void cmx270_init(void);
/* reserve IRQs for IT8152 */
#define CMX2XX_NR_IRQS (IRQ_BOARD_START + 40)
/* virtual addresses for statically mapped regions */
#define CMX2XX_VIRT_BASE (void __iomem *)(0xe8000000)
#define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE)
/* physical address if local-bus attached devices */
#define CMX255_DM9000_PHYS_BASE (PXA_CS1_PHYS + (8 << 22))
#define CMX270_DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22))
/* leds */
#define CMX255_GPIO_RED (27)
#define CMX255_GPIO_GREEN (32)
#define CMX270_GPIO_RED (93)
#define CMX270_GPIO_GREEN (94)
/* GPIO IRQ usage */
#define GPIO22_ETHIRQ (22)
#define GPIO10_ETHIRQ (10)
#define CMX255_GPIO_IT8152_IRQ (0)
#define CMX270_GPIO_IT8152_IRQ (22)
#define CMX255_ETHIRQ PXA_GPIO_TO_IRQ(GPIO22_ETHIRQ)
#define CMX270_ETHIRQ PXA_GPIO_TO_IRQ(GPIO10_ETHIRQ)
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
static struct resource cmx255_dm9000_resource[] = {
[0] = {
.start = CMX255_DM9000_PHYS_BASE,
.end = CMX255_DM9000_PHYS_BASE + 3,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CMX255_DM9000_PHYS_BASE + 4,
.end = CMX255_DM9000_PHYS_BASE + 4 + 500,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = CMX255_ETHIRQ,
.end = CMX255_ETHIRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct resource cmx270_dm9000_resource[] = {
[0] = {
.start = CMX270_DM9000_PHYS_BASE,
.end = CMX270_DM9000_PHYS_BASE + 3,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CMX270_DM9000_PHYS_BASE + 8,
.end = CMX270_DM9000_PHYS_BASE + 8 + 500,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = CMX270_ETHIRQ,
.end = CMX270_ETHIRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct dm9000_plat_data cmx270_dm9000_platdata = {
.flags = DM9000_PLATF_32BITONLY | DM9000_PLATF_NO_EEPROM,
};
static struct platform_device cmx2xx_dm9000_device = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(cmx270_dm9000_resource),
.dev = {
.platform_data = &cmx270_dm9000_platdata,
}
};
static void __init cmx2xx_init_dm9000(void)
{
if (cpu_is_pxa25x())
cmx2xx_dm9000_device.resource = cmx255_dm9000_resource;
else
cmx2xx_dm9000_device.resource = cmx270_dm9000_resource;
platform_device_register(&cmx2xx_dm9000_device);
}
#else
static inline void cmx2xx_init_dm9000(void) {}
#endif
/* UCB1400 touchscreen controller */
#if defined(CONFIG_TOUCHSCREEN_UCB1400) || defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
static struct platform_device cmx2xx_ts_device = {
.name = "ucb1400_core",
.id = -1,
};
static void __init cmx2xx_init_touchscreen(void)
{
platform_device_register(&cmx2xx_ts_device);
}
#else
static inline void cmx2xx_init_touchscreen(void) {}
#endif
/* CM-X270 LEDs */
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
static struct gpio_led cmx2xx_leds[] = {
[0] = {
.name = "cm-x2xx:red",
.default_trigger = "nand-disk",
.active_low = 1,
},
[1] = {
.name = "cm-x2xx:green",
.default_trigger = "heartbeat",
.active_low = 1,
},
};
static struct gpio_led_platform_data cmx2xx_gpio_led_pdata = {
.num_leds = ARRAY_SIZE(cmx2xx_leds),
.leds = cmx2xx_leds,
};
static struct platform_device cmx2xx_led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &cmx2xx_gpio_led_pdata,
},
};
static void __init cmx2xx_init_leds(void)
{
if (cpu_is_pxa25x()) {
cmx2xx_leds[0].gpio = CMX255_GPIO_RED;
cmx2xx_leds[1].gpio = CMX255_GPIO_GREEN;
} else {
cmx2xx_leds[0].gpio = CMX270_GPIO_RED;
cmx2xx_leds[1].gpio = CMX270_GPIO_GREEN;
}
platform_device_register(&cmx2xx_led_device);
}
#else
static inline void cmx2xx_init_leds(void) {}
#endif
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
/*
Display definitions
keep these for backwards compatibility, although symbolic names (as
e.g. in lpd270.c) looks better
*/
#define MTYPE_STN320x240 0
#define MTYPE_TFT640x480 1
#define MTYPE_CRT640x480 2
#define MTYPE_CRT800x600 3
#define MTYPE_TFT320x240 6
#define MTYPE_STN640x480 7
static struct pxafb_mode_info generic_stn_320x240_mode = {
.pixclock = 76923,
.bpp = 8,
.xres = 320,
.yres = 240,
.hsync_len = 3,
.vsync_len = 2,
.left_margin = 3,
.upper_margin = 0,
.right_margin = 3,
.lower_margin = 0,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_stn_320x240 = {
.modes = &generic_stn_320x240_mode,
.num_modes = 1,
.lcd_conn = LCD_COLOR_STN_8BPP | LCD_PCLK_EDGE_FALL |\
LCD_AC_BIAS_FREQ(0xff),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_tft_640x480_mode = {
.pixclock = 38461,
.bpp = 8,
.xres = 640,
.yres = 480,
.hsync_len = 60,
.vsync_len = 2,
.left_margin = 70,
.upper_margin = 10,
.right_margin = 70,
.lower_margin = 5,
.sync = 0,
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_tft_640x480 = {
.modes = &generic_tft_640x480_mode,
.num_modes = 1,
.lcd_conn = LCD_COLOR_TFT_8BPP | LCD_PCLK_EDGE_FALL |\
LCD_AC_BIAS_FREQ(0xff),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_crt_640x480_mode = {
.pixclock = 38461,
.bpp = 8,
.xres = 640,
.yres = 480,
.hsync_len = 63,
.vsync_len = 2,
.left_margin = 81,
.upper_margin = 33,
.right_margin = 16,
.lower_margin = 10,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_crt_640x480 = {
.modes = &generic_crt_640x480_mode,
.num_modes = 1,
.lcd_conn = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_crt_800x600_mode = {
.pixclock = 28846,
.bpp = 8,
.xres = 800,
.yres = 600,
.hsync_len = 63,
.vsync_len = 2,
.left_margin = 26,
.upper_margin = 21,
.right_margin = 26,
.lower_margin = 11,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_crt_800x600 = {
.modes = &generic_crt_800x600_mode,
.num_modes = 1,
.lcd_conn = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_tft_320x240_mode = {
.pixclock = 134615,
.bpp = 16,
.xres = 320,
.yres = 240,
.hsync_len = 63,
.vsync_len = 7,
.left_margin = 75,
.upper_margin = 0,
.right_margin = 15,
.lower_margin = 15,
.sync = 0,
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_tft_320x240 = {
.modes = &generic_tft_320x240_mode,
.num_modes = 1,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_AC_BIAS_FREQ(0xff),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_stn_640x480_mode = {
.pixclock = 57692,
.bpp = 8,
.xres = 640,
.yres = 480,
.hsync_len = 4,
.vsync_len = 2,
.left_margin = 10,
.upper_margin = 5,
.right_margin = 10,
.lower_margin = 5,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_stn_640x480 = {
.modes = &generic_stn_640x480_mode,
.num_modes = 1,
.lcd_conn = LCD_COLOR_STN_8BPP | LCD_AC_BIAS_FREQ(0xff),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mach_info *cmx2xx_display = &generic_crt_640x480;
static int __init cmx2xx_set_display(char *str)
{
int disp_type = simple_strtol(str, NULL, 0);
switch (disp_type) {
case MTYPE_STN320x240:
cmx2xx_display = &generic_stn_320x240;
break;
case MTYPE_TFT640x480:
cmx2xx_display = &generic_tft_640x480;
break;
case MTYPE_CRT640x480:
cmx2xx_display = &generic_crt_640x480;
break;
case MTYPE_CRT800x600:
cmx2xx_display = &generic_crt_800x600;
break;
case MTYPE_TFT320x240:
cmx2xx_display = &generic_tft_320x240;
break;
case MTYPE_STN640x480:
cmx2xx_display = &generic_stn_640x480;
break;
default: /* fallback to CRT 640x480 */
cmx2xx_display = &generic_crt_640x480;
break;
}
return 1;
}
/*
This should be done really early to get proper configuration for
frame buffer.
Indeed, pxafb parameters can be used istead, but CM-X2XX bootloader
has limitied line length for kernel command line, and also it will
break compatibitlty with proprietary releases already in field.
*/
__setup("monitor=", cmx2xx_set_display);
static void __init cmx2xx_init_display(void)
{
pxa_set_fb_info(NULL, cmx2xx_display);
}
#else
static inline void cmx2xx_init_display(void) {}
#endif
#ifdef CONFIG_PM
static unsigned long sleep_save_msc[10];
static int cmx2xx_suspend(void)
{
cmx2xx_pci_suspend();
/* save MSC registers */
sleep_save_msc[0] = __raw_readl(MSC0);
sleep_save_msc[1] = __raw_readl(MSC1);
sleep_save_msc[2] = __raw_readl(MSC2);
/* setup power saving mode registers */
PCFR = 0x0;
PSLR = 0xff400000;
PMCR = 0x00000005;
PWER = 0x80000000;
PFER = 0x00000000;
PRER = 0x00000000;
PGSR0 = 0xC0018800;
PGSR1 = 0x004F0002;
PGSR2 = 0x6021C000;
PGSR3 = 0x00020000;
return 0;
}
static void cmx2xx_resume(void)
{
cmx2xx_pci_resume();
/* restore MSC registers */
__raw_writel(sleep_save_msc[0], MSC0);
__raw_writel(sleep_save_msc[1], MSC1);
__raw_writel(sleep_save_msc[2], MSC2);
}
static struct syscore_ops cmx2xx_pm_syscore_ops = {
.resume = cmx2xx_resume,
.suspend = cmx2xx_suspend,
};
static int __init cmx2xx_pm_init(void)
{
register_syscore_ops(&cmx2xx_pm_syscore_ops);
return 0;
}
#else
static int __init cmx2xx_pm_init(void) { return 0; }
#endif
#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
static void __init cmx2xx_init_ac97(void)
{
pxa_set_ac97_info(NULL);
}
#else
static inline void cmx2xx_init_ac97(void) {}
#endif
static void __init cmx2xx_init(void)
{
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
cmx2xx_pm_init();
if (cpu_is_pxa25x())
cmx255_init();
else
cmx270_init();
cmx2xx_init_dm9000();
cmx2xx_init_display();
cmx2xx_init_ac97();
cmx2xx_init_touchscreen();
cmx2xx_init_leds();
regulator_has_full_constraints();
}
static void __init cmx2xx_init_irq(void)
{
if (cpu_is_pxa25x()) {
pxa25x_init_irq();
cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ);
} else {
pxa27x_init_irq();
cmx2xx_pci_init_irq(CMX270_GPIO_IT8152_IRQ);
}
}
#ifdef CONFIG_PCI
/* Map PCI companion statically */
static struct map_desc cmx2xx_io_desc[] __initdata = {
[0] = { /* PCI bridge */
.virtual = (unsigned long)CMX2XX_IT8152_VIRT,
.pfn = __phys_to_pfn(PXA_CS4_PHYS),
.length = SZ_64M,
.type = MT_DEVICE
},
};
static void __init cmx2xx_map_io(void)
{
if (cpu_is_pxa25x())
pxa25x_map_io();
if (cpu_is_pxa27x())
pxa27x_map_io();
iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc));
it8152_base_address = CMX2XX_IT8152_VIRT;
}
#else
static void __init cmx2xx_map_io(void)
{
if (cpu_is_pxa25x())
pxa25x_map_io();
if (cpu_is_pxa27x())
pxa27x_map_io();
}
#endif
MACHINE_START(ARMCORE, "Compulab CM-X2XX")
.atag_offset = 0x100,
.map_io = cmx2xx_map_io,
.nr_irqs = CMX2XX_NR_IRQS,
.init_irq = cmx2xx_init_irq,
/* NOTE: pxa25x_handle_irq() works on PXA27x w/o camera support */
.handle_irq = pxa25x_handle_irq,
.init_time = pxa_timer_init,
.init_machine = cmx2xx_init,
#ifdef CONFIG_PCI
.dma_zone_size = SZ_64M,
#endif
.restart = pxa_restart,
MACHINE_END

1286
arch/arm/mach-pxa/em-x270.c
View File

File diff suppressed because it is too large Load Diff

18
arch/arm/mach-pxa/include/mach/io.h
View File

@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-pxa/include/mach/io.h
*
* Copied from asm/arch/sa1100/io.h
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) __typesafe_io(a)
#endif

11
arch/arm/mach-realtek/Kconfig Normal file
View File

@ -0,0 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-or-later
menuconfig ARCH_REALTEK
bool "Realtek SoCs"
depends on ARCH_MULTI_V7
select ARM_GIC
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
select GENERIC_IRQ_CHIP
select RESET_CONTROLLER
help
This enables support for the Realtek RTD1195 SoC family.

2
arch/arm/mach-realtek/Makefile Normal file
View File

@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-or-later
obj-y += rtd1195.o

40
arch/arm/mach-realtek/rtd1195.c Normal file
View File

@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Realtek RTD1195
*
* Copyright (c) 2017-2019 Andreas Färber
*/
#include <linux/memblock.h>
#include <asm/mach/arch.h>
static void __init rtd1195_memblock_remove(phys_addr_t base, phys_addr_t size)
{
int ret;
ret = memblock_remove(base, size);
if (ret)
pr_err("Failed to remove memblock %pa (%d)\n", &base, ret);
}
static void __init rtd1195_reserve(void)
{
/* Exclude boot ROM from RAM */
rtd1195_memblock_remove(0x00000000, 0x0000a800);
/* Exclude peripheral register spaces from RAM */
rtd1195_memblock_remove(0x18000000, 0x00070000);
rtd1195_memblock_remove(0x18100000, 0x01000000);
}
static const char *const rtd1195_dt_compat[] __initconst = {
"realtek,rtd1195",
NULL
};
DT_MACHINE_START(rtd1195, "Realtek RTD1195")
.dt_compat = rtd1195_dt_compat,
.reserve = rtd1195_reserve,
.l2c_aux_val = 0x0,
.l2c_aux_mask = ~0x0,
MACHINE_END

10
arch/arm/mach-realview/Kconfig
View File

@ -6,7 +6,6 @@ menuconfig ARCH_REALVIEW
select ARM_GIC
select ARM_TIMER_SP804
select CLK_SP810
select COMMON_CLK_VERSATILE
select GPIO_PL061 if GPIOLIB
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
@ -16,12 +15,10 @@ menuconfig ARCH_REALVIEW
select MACH_REALVIEW_EB if ARCH_MULTI_V5
select MFD_SYSCON
select PLAT_VERSATILE
select PLAT_VERSATILE_SCHED_CLOCK
select POWER_RESET
select POWER_RESET_VERSATILE
select POWER_SUPPLY
select SOC_REALVIEW
select USE_OF
help
This enables support for ARM Ltd RealView boards.
@ -56,8 +53,6 @@ config REALVIEW_EB_ARM1176
config REALVIEW_EB_A9MP
bool "Support Multicore Cortex-A9 Tile"
depends on MACH_REALVIEW_EB && ARCH_MULTI_V7
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
Enable support for the Cortex-A9MPCore tile fitted to the
Realview(R) Emulation Baseboard platform.
@ -66,7 +61,6 @@ config REALVIEW_EB_ARM11MP
bool "Support ARM11MPCore Tile"
depends on MACH_REALVIEW_EB && ARCH_MULTI_V6
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
Enable support for the ARM11MPCore tile fitted to the Realview(R)
Emulation Baseboard platform.
@ -75,7 +69,6 @@ config MACH_REALVIEW_PB11MP
bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
depends on ARCH_MULTI_V6
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
Include support for the ARM(R) RealView(R) Platform Baseboard for
the ARM11MPCore. This platform has an on-board ARM11MPCore and has
@ -87,7 +80,6 @@ config MACH_REALVIEW_PB1176
depends on ARCH_MULTI_V6
select CPU_V6
select HAVE_TCM
select MIGHT_HAVE_CACHE_L2X0
help
Include support for the ARM(R) RealView(R) Platform Baseboard for
ARM1176JZF-S.
@ -103,8 +95,6 @@ config MACH_REALVIEW_PBA8
config MACH_REALVIEW_PBX
bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9"
depends on ARCH_MULTI_V7
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select ZONE_DMA
help
Include support for the ARM(R) RealView(R) Platform Baseboard

2
arch/arm/mach-rockchip/platsmp.c
View File

@ -180,7 +180,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
rsize = resource_size(&res);
if (rsize < trampoline_sz) {
pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
pr_err("%s: reserved block with size 0x%x is too small for trampoline size 0x%x\n",
__func__, rsize, trampoline_sz);
return -EINVAL;
}

2
arch/arm/mach-rockchip/rockchip.c
View File

@ -9,9 +9,9 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of_clk.h>
#include <linux/of_platform.h>
#include <linux/irqchip.h>
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

7
arch/arm/mach-s3c64xx/mach-crag6410-module.c
View File

@ -405,10 +405,9 @@ static int wlf_gf_module_probe(struct i2c_client *i2c,
gf_mods[i].name, rev + 1);
for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
if (!i2c_new_device(i2c->adapter,
&(gf_mods[i].i2c_devs[j])))
dev_err(&i2c->dev,
"Failed to register dev: %d\n", ret);
if (IS_ERR(i2c_new_client_device(i2c->adapter,
&(gf_mods[i].i2c_devs[j]))))
dev_err(&i2c->dev, "Failed to register\n");
}
spi_register_board_info(gf_mods[i].spi_devs,

2
arch/arm/mach-shmobile/setup-rcar-gen2.c
View File

@ -24,6 +24,7 @@
#include "rcar-gen2.h"
static const struct of_device_id cpg_matches[] __initconst = {
{ .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
@ -209,6 +210,7 @@ DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)")
MACHINE_END
static const char * const rz_g1_boards_compat_dt[] __initconst = {
"renesas,r8a7742",
"renesas,r8a7743",
"renesas,r8a7744",
"renesas,r8a7745",

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