dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs. Signed-off-by: Guido Günther <agx@sigxcpu.org> Tested-by: Robert Chiras <robert.chiras@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/147ffc1e4dee3a623e5dca25d84565d386a34112.1586427783.git.agx@sigxcpu.org
This commit is contained in:
Guido Günther
Sam Ravnborg
parent
b22b51a034
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Northwest Logic MIPI-DSI controller on i.MX SoCs
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maintainers:
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- Guido Gúnther <agx@sigxcpu.org>
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- Robert Chiras <robert.chiras@nxp.com>
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description: |
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NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
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the SOCs NWL MIPI-DSI host controller.
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properties:
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compatible:
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const: fsl,imx8mq-nwl-dsi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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clocks:
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items:
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- description: DSI core clock
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- description: RX_ESC clock (used in escape mode)
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- description: TX_ESC clock (used in escape mode)
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- description: PHY_REF clock
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- description: LCDIF clock
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clock-names:
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items:
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- const: core
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- const: rx_esc
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- const: tx_esc
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- const: phy_ref
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- const: lcdif
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mux-controls:
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description:
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mux controller node to use for operating the input mux
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phys:
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maxItems: 1
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description:
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A phandle to the phy module representing the DPHY
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phy-names:
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items:
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- const: dphy
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power-domains:
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maxItems: 1
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resets:
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items:
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- description: dsi byte reset line
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- description: dsi dpi reset line
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- description: dsi esc reset line
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- description: dsi pclk reset line
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reset-names:
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items:
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- const: byte
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- const: dpi
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- const: esc
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- const: pclk
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ports:
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type: object
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description:
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A node containing DSI input & output port nodes with endpoint
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definitions as documented in
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Documentation/devicetree/bindings/graph.txt.
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properties:
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port@0:
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type: object
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description:
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Input port node to receive pixel data from the
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display controller. Exactly one endpoint must be
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specified.
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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endpoint@0:
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description: sub-node describing the input from LCDIF
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type: object
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endpoint@1:
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description: sub-node describing the input from DCSS
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type: object
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reg:
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const: 0
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required:
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- '#address-cells'
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- '#size-cells'
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- reg
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oneOf:
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- required:
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- endpoint@0
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- required:
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- endpoint@1
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additionalProperties: false
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port@1:
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type: object
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description:
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DSI output port node to the panel or the next bridge
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in the chain
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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required:
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- '#address-cells'
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- '#size-cells'
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- port@0
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- port@1
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additionalProperties: false
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patternProperties:
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"^panel@[0-9]+$":
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type: object
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required:
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- '#address-cells'
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- '#size-cells'
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- clock-names
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- clocks
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- compatible
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- interrupts
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- mux-controls
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- phy-names
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- phys
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- ports
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- reg
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- reset-names
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mq-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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mipi_dsi: mipi_dsi@30a00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8mq-nwl-dsi";
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reg = <0x30A00000 0x300>;
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clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
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<&clk IMX8MQ_CLK_DSI_AHB>,
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<&clk IMX8MQ_CLK_DSI_IPG_DIV>,
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<&clk IMX8MQ_CLK_DSI_PHY_REF>,
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<&clk IMX8MQ_CLK_LCDIF_PIXEL>;
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clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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mux-controls = <&mux 0>;
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power-domains = <&pgc_mipi>;
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resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
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<&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
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<&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
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<&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
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reset-names = "byte", "dpi", "esc", "pclk";
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phys = <&dphy>;
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phy-names = "dphy";
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panel@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "rocktech,jh057n00900";
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reg = <0>;
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port@0 {
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reg = <0>;
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panel_in: endpoint {
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remote-endpoint = <&mipi_dsi_out>;
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#size-cells = <0>;
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#address-cells = <1>;
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reg = <0>;
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mipi_dsi_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&lcdif_mipi_dsi>;
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};
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};
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port@1 {
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reg = <1>;
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mipi_dsi_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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};
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