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ARM: SoC fixes for v4.3-rc 

Our first real batch of fixes this release cycle. There's a collection of
 them here:
 
 - A fixup for a build breakage that hits on arm64 allmodconfig in QCOM SCM
   firmware drivers
 - MMC fixes for OMAP that had quite a bit of breakage this merge window.
 - Misc build/warning fixes on PXA and OMAP
 - A couple of minor fixes for Beagleboard X15 which is now starting to see
   a few more users in the wild
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWB3+pAAoJEIwa5zzehBx36sAP/idEfXiZJiriXSLcU1AkWo23
 PAeIiIpENn6tbYrI0ogN+I63uNE9TkrWP/us9ZlPqQJOG29DVyol0YuAEmT3VSeo
 hColJInE2450fPxFw7hKOWnQ2En30fI5cIHUHzDNJl1Tn2liE4K2FuenSLmf34KH
 XQ2VkNMjj8uM9C0UMy/Tescm3r4LYKk9NXVG+oWDkw1PVdFMsBIE1Vo7KLWGJ6Ta
 Ig6Ub2A2ag1usJjjaTNJsbU4WRxHk37/r+psDzyTTxhp9ulS0uer84K7pqW7AVWn
 NsTUI83z3grKvnQrlTNKu7WCJH4Q+Xgru05mV3yhEoza+X7RhMAWX7zAgq7D3fDX
 mRT4L5RLZJZ8GDsWS35BMxBOOi3uxfPUtT1k2YobJeQYKaHaE06S5K9BMbaPCV6M
 d7ShNGuESz9RRLRDQFYaCqhZHyYoWxS1o0gczoEqB9/piPS7Fv7rQ1tujEU+/o8r
 8uwN6zYmcUJJykn+NxPP6Qskc4vWT+nQaGOp7YKkUFrh6wgssIOlU1HoYfPssjbM
 A0LHFZ1vRNFxtdnPhSi9A5IvVg4ST2G47MSV46ifplWzGyJXbDxuBV1/sCxbfUFn
 FRXt5FakkkbhTm/PsC9Dd/CYBx1HMlGoAP6nvmMccmmvWKTfEzjkuyTDhPWGihZN
 ZSos4D3kdlKnEtRZYfrx
 =ThcO
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "Our first real batch of fixes this release cycle.  Nothing really
  concerning, and diffstat is a bit inflated due to some DT contents
  moving around on STi platforms.

  There's a collection of them here:

   - A fixup for a build breakage that hits on arm64 allmodconfig in
     QCOM SCM firmware drivers
   - MMC fixes for OMAP that had quite a bit of breakage this merge
     window.
   - Misc build/warning fixes on PXA and OMAP
   - A couple of minor fixes for Beagleboard X15 which is now starting
     to see a few more users in the wild"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (31 commits)
  ARM: sti: dt: adapt DT to fix probe/bind issues in DRM driver
  ARM: dts: fix omap2+ address translation for pbias
  firmware: qcom: scm: Add function stubs for ARM64
  ARM: dts: am57xx-beagle-x15: use palmas-usb for USB2
  ARM: omap2plus_defconfig: enable GPIO_PCA953X
  ARM: dts: omap5-uevm.dts: fix i2c5 pinctrl offsets
  ARM: OMAP2+: AM43XX: Enable autoidle for clks in am43xx_init_late
  ARM: dts: am57xx-beagle-x15: Update Phy supplies
  ARM: pxa: balloon3: Fix build error
  ARM: dts: Fixup model name for HP t410 dts
  ARM: dts: DRA7: fix a typo in ethernet
  ARM: omap2plus_defconfig: make PCF857x built-in
  ARM: dts: Use ti,pbias compatible string for pbias
  ARM: OMAP5: Cleanup options for SoC only build
  ARM: DRA7: Select missing options for SoC only build
  ARM: OMAP2+: board-generic: Remove stale of_irq macros
  ARM: OMAP4+: PM: erratum is used by OMAP5 and DRA7 as well
  ARM: dts: omap3-igep: Move eth IRQ pinmux to IGEPv2 common dtsi
  ARM: dts: am57xx-beagle-x15: Add wakeup irq for mcp79410
  ARM: dts: am335x-phycore-som: Fix mpu voltage
  ...
This commit is contained in:
Linus Torvalds 2015-09-27 06:45:18 -04:00
parent 69ea8b8577 e46fc90ec2
commit 685b5f1de6
34 changed files with 270 additions and 154 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/am335x-phycore-som.dtsi
View File

@ -252,10 +252,10 @@
};
vdd1_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1312500>;
regulator-max-microvolt = <1378000>;
regulator-boot-on;
regulator-always-on;
};

46
arch/arm/boot/dts/am57xx-beagle-x15.dts
View File

@ -98,13 +98,6 @@
pinctrl-0 = <&extcon_usb1_pins>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio7 24 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&extcon_usb2_pins>;
};
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
@ -326,12 +319,6 @@
>;
};
extcon_usb2_pins: extcon_usb2_pins {
pinctrl-single,pins = <
0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
0x3b0 (PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
@ -432,7 +419,7 @@
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
/* VDDA_1V8_PHYA */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -440,6 +427,15 @@
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_1V8_PHYB */
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo9_reg: ldo9 {
/* VDD_RTC */
regulator-name = "ldo9";
@ -495,6 +491,14 @@
gpio-controller;
#gpio-cells = <2>;
};
extcon_usb2: tps659038_usb {
compatible = "ti,palmas-usb-vid";
ti,enable-vbus-detection;
ti,enable-id-detection;
id-gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>;
};
};
tmp102: tmp102@48 {
@ -517,7 +521,8 @@
mcp_rtc: rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */
interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
<&dra7_pmx_core 0x424>;
pinctrl-names = "default";
pinctrl-0 = <&mcp79410_pins_default>;
@ -579,7 +584,6 @@
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&ldo1_reg>;
vmmc_aux-supply = <&vdd_3v3>;
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
};
@ -623,6 +627,14 @@
};
&usb2 {
/*
* Stand alone usage is peripheral only.
* However, with some resistor modifications
* this port can be used via expansion connectors
* as "host" or "dual-role". If so, provide
* the necessary dr_mode override in the expansion
* board's DT.
*/
dr_mode = "peripheral";
};
@ -681,7 +693,7 @@
&hdmi {
status = "ok";
vdda-supply = <&ldo3_reg>;
vdda-supply = <&ldo4_reg>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;

4
arch/arm/boot/dts/dm8148-evm.dts
View File

@ -19,10 +19,10 @@
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
phy-mode = "rgmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
phy-mode = "rgmii";
};

6
arch/arm/boot/dts/dm8148-t410.dts
View File

@ -8,7 +8,7 @@
#include "dm814x.dtsi"
/ {
model = "DM8148 EVM";
model = "HP t410 Smart Zero Client";
compatible = "hp,t410", "ti,dm8148";
memory {
@ -19,10 +19,10 @@
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
phy-mode = "rgmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
phy-mode = "rgmii";
};

8
arch/arm/boot/dts/dm814x.dtsi
View File

@ -181,9 +181,9 @@
ti,hwmods = "timer3";
};
control: control@160000 {
control: control@140000 {
compatible = "ti,dm814-scm", "simple-bus";
reg = <0x160000 0x16d000>;
reg = <0x140000 0x16d000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x160000 0x16d000>;
@ -321,9 +321,9 @@
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@0x48160650 {
phy_sel: cpsw-phy-sel@48140650 {
compatible = "ti,am3352-cpsw-phy-sel";
reg= <0x48160650 0x4>;
reg= <0x48140650 0x4>;
reg-names = "gmii-sel";
};
};

5
arch/arm/boot/dts/dra7.dtsi
View File

@ -120,9 +120,10 @@
reg = <0x0 0x1400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x1400>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
compatible = "ti,pbias-dra7", "ti,pbias-omap";
reg = <0xe00 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap5 {
@ -1417,7 +1418,7 @@
ti,irqs-safe-map = <0>;
};
mac: ethernet@4a100000 {
mac: ethernet@48484000 {
compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;

3
arch/arm/boot/dts/omap2430.dtsi
View File

@ -56,6 +56,7 @@
reg = <0x270 0x240>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x270 0x240>;
scm_clocks: clocks {
#address-cells = <1>;
@ -63,7 +64,7 @@
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
compatible = "ti,pbias-omap2", "ti,pbias-omap";
reg = <0x230 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap2430 {

2
arch/arm/boot/dts/omap3-beagle.dts
View File

@ -202,7 +202,7 @@
tfp410_pins: pinmux_tfp410_pins {
pinctrl-single,pins = <
0x194 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
>;
};

6
arch/arm/boot/dts/omap3-igep.dtsi
View File

@ -78,12 +78,6 @@
>;
};
smsc9221_pins: pinmux_smsc9221_pins {
pinctrl-single,pins = <
0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */

6
arch/arm/boot/dts/omap3-igep0020-common.dtsi
View File

@ -156,6 +156,12 @@
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
>;
};
smsc9221_pins: pinmux_smsc9221_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
>;
};
};
&omap3_pmx_core2 {

25
arch/arm/boot/dts/omap3.dtsi
View File

@ -113,10 +113,22 @@
};
scm_conf: scm_conf@270 {
compatible = "syscon";
compatible = "syscon", "simple-bus";
reg = <0x270 0x330>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x270 0x330>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap3", "ti,pbias-omap";
reg = <0x2b0 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap2430 {
regulator-name = "pbias_mmc_omap2430";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
scm_clocks: clocks {
#address-cells = <1>;
@ -202,17 +214,6 @@
dma-requests = <96>;
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x2b0 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap2430 {
regulator-name = "pbias_mmc_omap2430";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
gpio1: gpio@48310000 {
compatible = "ti,omap3-gpio";
reg = <0x48310000 0x200>;

3
arch/arm/boot/dts/omap4.dtsi
View File

@ -196,9 +196,10 @@
reg = <0x5a0 0x170>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5a0 0x170>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
compatible = "ti,pbias-omap4", "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap4_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap4 {

4
arch/arm/boot/dts/omap5-uevm.dts
View File

@ -174,8 +174,8 @@
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins = <
0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */
0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */
0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */
0x188 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */
>;
};

3
arch/arm/boot/dts/omap5.dtsi
View File

@ -185,9 +185,10 @@
reg = <0x5a0 0xec>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5a0 0xec>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
compatible = "ti,pbias-omap5", "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap5_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap5 {

1
arch/arm/boot/dts/rk3288-veyron.dtsi
View File

@ -158,6 +158,7 @@
};
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
};

4
arch/arm/boot/dts/stih407.dtsi
View File

@ -103,7 +103,7 @@
<&clk_s_d0_quadfs 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>;
ranges;
};
sti-hdmi@8d04000 {
compatible = "st,stih407-hdmi";
@ -129,7 +129,6 @@
reset-names = "hdmi";
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
ddc = <&hdmiddc>;
};
sti-hda@8d02000 {
@ -147,5 +146,4 @@
};
};
};
};
};

4
arch/arm/boot/dts/stih410.dtsi
View File

@ -178,7 +178,7 @@
<&clk_s_d0_quadfs 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>;
ranges;
};
sti-hdmi@8d04000 {
compatible = "st,stih407-hdmi";
@ -204,7 +204,6 @@
reset-names = "hdmi";
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
ddc = <&hdmiddc>;
};
sti-hda@8d02000 {
@ -221,7 +220,6 @@
<&clk_s_d2_quadfs 1>;
};
};
};
bdisp0:bdisp@9f10000 {
compatible = "st,stih407-bdisp";

5
arch/arm/configs/omap2plus_defconfig
View File

@ -240,7 +240,8 @@ CONFIG_SSI_PROTOCOL=m
CONFIG_PINCTRL_SINGLE=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_PCA953X=m
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_TWL4030=y
CONFIG_GPIO_PALMAS=y
CONFIG_W1=m
@ -350,6 +351,8 @@ CONFIG_USB_MUSB_HDRC=m
CONFIG_USB_MUSB_OMAP2PLUS=m
CONFIG_USB_MUSB_AM35X=m
CONFIG_USB_MUSB_DSPS=m
CONFIG_USB_INVENTRA_DMA=y
CONFIG_USB_TI_CPPI41_DMA=y
CONFIG_USB_DWC3=m
CONFIG_USB_TEST=m
CONFIG_AM335X_PHY_USB=y

6
arch/arm/mach-omap2/Kconfig
View File

@ -44,10 +44,11 @@ config SOC_OMAP5
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_ARM_ARCH_TIMER
select ARM_ERRATA_798181 if SMP
select OMAP_INTERCONNECT
select OMAP_INTERCONNECT_BARRIER
select PM_OPP if PM
config SOC_AM33XX
bool "TI AM33XX"
@ -70,10 +71,13 @@ config SOC_DRA7XX
select ARCH_OMAP2PLUS
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select HAVE_ARM_SCU if SMP
select HAVE_ARM_ARCH_TIMER
select IRQ_CROSSBAR
select ARM_ERRATA_798181 if SMP
select OMAP_INTERCONNECT
select OMAP_INTERCONNECT_BARRIER
select PM_OPP if PM
config ARCH_OMAP2PLUS
bool

7
arch/arm/mach-omap2/board-generic.c
View File

@ -20,13 +20,6 @@
#include "common.h"
#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
#define intc_of_init NULL
#endif
#ifndef CONFIG_ARCH_OMAP4
#define gic_of_init NULL
#endif
static const struct of_device_id omap_dt_match_table[] __initconst = {
{ .compatible = "simple-bus", },
{ .compatible = "ti,omap-infra", },

8
arch/arm/mach-omap2/id.c
View File

@ -653,8 +653,12 @@ void __init dra7xxx_check_revision(void)
omap_revision = DRA752_REV_ES1_0;
break;
case 1:
default:
omap_revision = DRA752_REV_ES1_1;
break;
case 2:
default:
omap_revision = DRA752_REV_ES2_0;
break;
}
break;
@ -674,7 +678,7 @@ void __init dra7xxx_check_revision(void)
/* Unknown default to latest silicon rev as default*/
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
__func__, idcode, hawkeye, rev);
omap_revision = DRA752_REV_ES1_1;
omap_revision = DRA752_REV_ES2_0;
}
sprintf(soc_name, "DRA%03x", omap_rev() >> 16);

1
arch/arm/mach-omap2/io.c
View File

@ -676,6 +676,7 @@ void __init am43xx_init_early(void)
void __init am43xx_init_late(void)
{
omap_common_late_init();
omap2_clk_enable_autoidle_all();
}
#endif

3
arch/arm/mach-omap2/omap_device.c
View File

@ -901,7 +901,8 @@ static int __init omap_device_late_idle(struct device *dev, void *data)
if (od->hwmods[i]->flags & HWMOD_INIT_NO_IDLE)
return 0;
if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER &&
od->_driver_status != BUS_NOTIFY_BIND_DRIVER) {
if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
dev_warn(dev, "%s: enabled but no driver. Idling\n",
__func__);

3
arch/arm/mach-omap2/pm.h
View File

@ -103,7 +103,8 @@ static inline void enable_omap3630_toggle_l2_on_restore(void) { }
#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0)
#define PM_OMAP4_CPU_OSWR_DISABLE (1 << 1)
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) ||\
defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
extern u16 pm44xx_errata;
#define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id))
#else

2
arch/arm/mach-omap2/soc.h
View File

@ -469,6 +469,8 @@ IS_OMAP_TYPE(3430, 0x3430)
#define DRA7XX_CLASS 0x07000000
#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))
#define DRA752_REV_ES2_0 (DRA7XX_CLASS | (0x52 << 16) | (0x20 << 8))
#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
void omap2xxx_check_revision(void);

8
arch/arm/mach-omap2/timer.c
View File

@ -297,12 +297,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
if (IS_ERR(src))
return PTR_ERR(src);
r = clk_set_parent(timer->fclk, src);
if (r < 0) {
pr_warn("%s: %s cannot set source\n", __func__, oh->name);
clk_put(src);
return r;
}
WARN(clk_set_parent(timer->fclk, src) < 0,
"Cannot set timer parent clock, no PLL clock driver?");
clk_put(src);

2
arch/arm/mach-omap2/vc.c
View File

@ -300,7 +300,7 @@ static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET);
if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) ||
(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL)) {
(val & OMAP3430_PRM_POLCTRL_OFFMODE_POL)) {
val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL;
val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL;
pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",

2
arch/arm/mach-pxa/balloon3.c
View File

@ -502,7 +502,7 @@ static void balloon3_irq_handler(struct irq_desc *desc)
balloon3_irq_enabled;
do {
struct irq_data *d = irq_desc_get_irq_data(desc);
struct irq_chip *chip = irq_data_get_chip(d);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int irq;
/* clear useless edge notification */

7
arch/arm/mach-pxa/include/mach/addr-map.h
View File

@ -43,6 +43,13 @@
* 0xf6200000..0xf6201000
*/
/*
* DFI Bus for NAND, PXA3xx only
*/
#define NAND_PHYS 0x43100000
#define NAND_VIRT IOMEM(0xf6300000)
#define NAND_SIZE 0x00100000
/*
* Internal Memory Controller (PXA27x and later)
*/

21
arch/arm/mach-pxa/pxa3xx.c
View File

@ -47,6 +47,13 @@ extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
#define ISRAM_START 0x5c000000
#define ISRAM_SIZE SZ_256K
/*
* NAND NFC: DFI bus arbitration subset
*/
#define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0))
#define NDCR_ND_ARB_EN (1 << 12)
#define NDCR_ND_ARB_CNTL (1 << 19)
static void __iomem *sram;
static unsigned long wakeup_src;
@ -362,7 +369,12 @@ static struct map_desc pxa3xx_io_desc[] __initdata = {
.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
.length = SMEMC_SIZE,
.type = MT_DEVICE
}
}, {
.virtual = (unsigned long)NAND_VIRT,
.pfn = __phys_to_pfn(NAND_PHYS),
.length = NAND_SIZE,
.type = MT_DEVICE
},
};
void __init pxa3xx_map_io(void)
@ -419,6 +431,13 @@ static int __init pxa3xx_init(void)
*/
ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
/*
* Disable DFI bus arbitration, to prevent a system bus lock if
* somebody disables the NAND clock (unused clock) while this
* bit remains set.
*/
NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
if ((ret = pxa_init_dma(IRQ_DMA, 32)))
return ret;

1
arch/arm/plat-pxa/ssp.c
View File

@ -107,7 +107,6 @@ static const struct of_device_id pxa_ssp_of_ids[] = {
{ .compatible = "mvrl,pxa168-ssp", .data = (void *) PXA168_SSP },
{ .compatible = "mrvl,pxa910-ssp", .data = (void *) PXA910_SSP },
{ .compatible = "mrvl,ce4100-ssp", .data = (void *) CE4100_SSP },
{ .compatible = "mrvl,lpss-ssp", .data = (void *) LPSS_SSP },
{ },
};
MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);

8
drivers/firmware/Kconfig
View File

@ -139,6 +139,14 @@ config QCOM_SCM
bool
depends on ARM || ARM64
config QCOM_SCM_32
def_bool y
depends on QCOM_SCM && ARM
config QCOM_SCM_64
def_bool y
depends on QCOM_SCM && ARM64
source "drivers/firmware/broadcom/Kconfig"
source "drivers/firmware/google/Kconfig"
source "drivers/firmware/efi/Kconfig"

3
drivers/firmware/Makefile
View File

@ -13,7 +13,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o
obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o
CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
obj-y += broadcom/

63
drivers/firmware/qcom_scm-64.c Normal file
View File

@ -0,0 +1,63 @@
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/qcom_scm.h>
/**
* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
* @entry: Entry point function for the cpus
* @cpus: The cpumask of cpus that will use the entry point
*
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
return -ENOTSUPP;
}
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
* @entry: Entry point function for the cpus
* @cpus: The cpumask of cpus that will use the entry point
*
* Set the Linux entry point for the SCM to transfer control to when coming
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
*/
int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
return -ENOTSUPP;
}
/**
* qcom_scm_cpu_power_down() - Power down the cpu
* @flags - Flags to flush cache
*
* This is an end point to power down cpu. If there was a pending interrupt,
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
void __qcom_scm_cpu_power_down(u32 flags)
{
}
int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id)
{
return -ENOTSUPP;
}
int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
{
return -ENOTSUPP;
}