ARM: tegra: Don't enable unused PLLs on resume from suspend
PLLC and PLLM are usually disabled on system suspend because all devices which use these PLLs are either suspended or switched away to other clock source. Don't enable unused PLLs on resume from suspend by keeping track of the enable-state of the PLLs across suspend-resume. Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Tested-by: Matt Merhar <mattmerhar@protonmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko
Thierry Reding
parent
5c8fe583cc
commit
680ae44526
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@ -43,11 +43,34 @@
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#define APB_MISC_XM2CFGCPADCTRL2 0x8e4
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#define APB_MISC_XM2CFGDPADCTRL2 0x8e8
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.macro pll_enable, rd, r_car_base, pll_base
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#define PLLC_STORE_MASK (1 << 0)
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#define PLLM_STORE_MASK (1 << 1)
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#define PLLP_STORE_MASK (1 << 2)
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.macro test_pll_state, rd, test_mask
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ldr \rd, tegra_pll_state
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tst \rd, #\test_mask
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.endm
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.macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask
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ldr \rd, [\r_car_base, #\pll_base]
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tst \rd, #(1 << 30)
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ldr \rd, tegra_pll_state
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biceq \rd, \rd, #\pll_mask
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orrne \rd, \rd, #\pll_mask
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adr \tmp, tegra_pll_state
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str \rd, [\tmp]
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.endm
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.macro pll_enable, rd, r_car_base, pll_base, test_mask
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test_pll_state \rd, \test_mask
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beq 1f
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ldr \rd, [\r_car_base, #\pll_base]
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tst \rd, #(1 << 30)
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orreq \rd, \rd, #(1 << 30)
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streq \rd, [\r_car_base, #\pll_base]
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1:
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.endm
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.macro emc_device_mask, rd, base
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@ -177,9 +200,9 @@ ENTRY(tegra20_lp1_reset)
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str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
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str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
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pll_enable r1, r0, CLK_RESET_PLLM_BASE
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pll_enable r1, r0, CLK_RESET_PLLP_BASE
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pll_enable r1, r0, CLK_RESET_PLLC_BASE
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pll_enable r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
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pll_enable r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
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pll_enable r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
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adr r2, tegra20_sdram_pad_address
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adr r4, tegra20_sdram_pad_save
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@ -270,6 +293,10 @@ tegra20_switch_cpu_to_clk32k:
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add r1, r1, #2
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wait_until r1, r7, r9
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store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
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store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
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store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
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/* disable PLLM, PLLP and PLLC */
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ldr r0, [r5, #CLK_RESET_PLLM_BASE]
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bic r0, r0, #(1 << 30)
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@ -396,6 +423,9 @@ tegra20_sdram_pad_save:
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.long 0
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.endr
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tegra_pll_state:
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.word 0x0
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.ltorg
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/* dummy symbol for end of IRAM */
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.align L1_CACHE_SHIFT
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@ -71,6 +71,13 @@
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#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
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#define PLLA_STORE_MASK (1 << 0)
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#define PLLC_STORE_MASK (1 << 1)
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#define PLLM_STORE_MASK (1 << 2)
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#define PLLP_STORE_MASK (1 << 3)
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#define PLLX_STORE_MASK (1 << 4)
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#define PLLM_PMC_STORE_MASK (1 << 5)
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.macro emc_device_mask, rd, base
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ldr \rd, [\base, #EMC_ADR_CFG]
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tst \rd, #0x1
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@ -87,7 +94,43 @@
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bne 1001b
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.endm
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.macro pll_enable, rd, r_car_base, pll_base, pll_misc
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.macro test_pll_state, rd, test_mask
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ldr \rd, tegra_pll_state
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tst \rd, #\test_mask
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.endm
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.macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask
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ldr \rd, [\r_car_base, #\pll_base]
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tst \rd, #(1 << 30)
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ldr \rd, tegra_pll_state
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biceq \rd, \rd, #\pll_mask
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orrne \rd, \rd, #\pll_mask
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adr \tmp, tegra_pll_state
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str \rd, [\tmp]
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.endm
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.macro store_pllm_pmc_state, rd, tmp, pmc_base
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ldr \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE]
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tst \rd, #(1 << 12)
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ldr \rd, tegra_pll_state
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biceq \rd, \rd, #PLLM_PMC_STORE_MASK
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orrne \rd, \rd, #PLLM_PMC_STORE_MASK
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adr \tmp, tegra_pll_state
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str \rd, [\tmp]
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.endm
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.macro pllm_pmc_enable, rd, pmc_base
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test_pll_state \rd, PLLM_PMC_STORE_MASK
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ldrne \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE]
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orrne \rd, \rd, #(1 << 12)
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strne \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE]
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.endm
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.macro pll_enable, rd, r_car_base, pll_base, pll_misc, test_mask
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test_pll_state \rd, \test_mask
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beq 1f
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ldr \rd, [\r_car_base, #\pll_base]
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tst \rd, #(1 << 30)
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orreq \rd, \rd, #(1 << 30)
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@ -102,13 +145,17 @@
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orr \rd, \rd, #(1 << 18)
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str \rd, [\r_car_base, #\pll_misc]
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.endif
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1:
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.endm
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.macro pll_locked, rd, r_car_base, pll_base
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.macro pll_locked, rd, r_car_base, pll_base, test_mask
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test_pll_state \rd, \test_mask
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beq 2f
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1:
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ldr \rd, [\r_car_base, #\pll_base]
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tst \rd, #(1 << 27)
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beq 1b
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2:
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.endm
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.macro pll_iddq_exit, rd, car, iddq, iddq_bit
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@ -342,34 +389,30 @@ ENTRY(tegra30_lp1_reset)
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/* enable PLLM via PMC */
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mov32 r2, TEGRA_PMC_BASE
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ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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orr r1, r1, #(1 << 12)
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str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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pllm_pmc_enable r1, r2
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pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
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pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
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pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
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pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0, PLLM_STORE_MASK
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pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK
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pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK
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b _pll_m_c_x_done
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_no_pll_iddq_exit:
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/* enable PLLM via PMC */
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mov32 r2, TEGRA_PMC_BASE
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ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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orr r1, r1, #(1 << 12)
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str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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pllm_pmc_enable r1, r2
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pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
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pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
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pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC, PLLM_STORE_MASK
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pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK
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_pll_m_c_x_done:
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pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
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pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
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pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC, PLLP_STORE_MASK
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pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC, PLLA_STORE_MASK
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pll_locked r1, r0, CLK_RESET_PLLM_BASE
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pll_locked r1, r0, CLK_RESET_PLLP_BASE
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pll_locked r1, r0, CLK_RESET_PLLA_BASE
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pll_locked r1, r0, CLK_RESET_PLLC_BASE
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pll_locked r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
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pll_locked r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
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pll_locked r1, r0, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
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pll_locked r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
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/*
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* CPUFreq driver could select other PLL for CPU. PLLX will be
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@ -380,7 +423,7 @@ _pll_m_c_x_done:
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cmp r1, #TEGRA30
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beq 1f
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pll_locked r1, r0, CLK_RESET_PLLX_BASE
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pll_locked r1, r0, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
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ldr r1, [r0, #CLK_RESET_PLLP_BASE]
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bic r1, r1, #(1<<31) @ disable PllP bypass
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@ -593,6 +636,9 @@ tegra_sdram_pad_save:
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.long 0
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.endr
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tegra_pll_state:
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.word 0x0
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/*
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* tegra30_tear_down_core
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*
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@ -641,6 +687,14 @@ tegra30_switch_cpu_to_clk32k:
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add r1, r1, #2
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wait_until r1, r7, r9
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/* store enable-state of PLLs */
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store_pll_state r0, r1, r5, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
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store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
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store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
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store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
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store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
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store_pllm_pmc_state r0, r1, r4
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/* disable PLLM via PMC in LP1 */
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ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
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bic r0, r0, #(1 << 12)
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