[ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call
Add s3c2412_gpio_set_sleepcfg() to allow the setting of the sleep configuration of the GPIO blocks. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -12,6 +12,7 @@ obj- :=
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obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
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obj-$(CONFIG_CPU_S3C2412) += irq.o
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obj-$(CONFIG_CPU_S3C2412) += clock.o
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obj-$(CONFIG_CPU_S3C2412) += gpio.o
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obj-$(CONFIG_S3C2412_DMA) += dma.o
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obj-$(CONFIG_S3C2412_PM) += pm.o sleep.o
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@ -0,0 +1,60 @@
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/* linux/arch/arm/mach-s3c2412/gpio.c
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*
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* Copyright (c) 2007 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* http://armlinux.simtec.co.uk/.
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*
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* S3C2412/S3C2413 specific GPIO support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/hardware.h>
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int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
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{
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void __iomem *base = S3C24XX_GPIO_BASE(pin);
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unsigned long offs = S3C2410_GPIO_OFFSET(pin);
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unsigned long flags;
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unsigned long slpcon;
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offs *= 2;
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if (pin < S3C2410_GPIO_BANKB)
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return -EINVAL;
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if (pin >= S3C2410_GPIO_BANKF &&
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pin <= S3C2410_GPIO_BANKG)
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return -EINVAL;
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if (pin > (S3C2410_GPIO_BANKH + 32))
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return -EINVAL;
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local_irq_save(flags);
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slpcon = __raw_readl(base + 0x0C);
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slpcon &= ~(3 << offs);
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slpcon |= state << offs;
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__raw_writel(slpcon, base + 0x0C);
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg);
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@ -99,6 +99,11 @@ extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
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#endif /* CONFIG_CPU_S3C2440 */
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#ifdef CONFIG_CPU_S3C2412
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extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
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#endif /* CONFIG_CPU_S3C2412 */
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#endif /* __ASSEMBLY__ */
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@ -1138,6 +1138,11 @@
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#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
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/* definitions for each pin bit */
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#define S3C2412_GPIO_SLPCON_LOW ( 0x00 )
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#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
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#define S3C2412_GPIO_SLPCON_IN ( 0x02 )
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#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
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#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
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#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2))
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#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
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