spmi: pmic_arb: add support for interrupt handling
The Qualcomm PMIC Arbiter, in addition to being a basic SPMI controller, also implements interrupt handling for slave devices. Note, this is outside the scope of SPMI, as SPMI leaves interrupt handling completely unspecified. Extend the driver to provide a irq_chip implementation and chained irq handling which allows for these interrupts to be used. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Josh Cartwright
Greg Kroah-Hartman
parent
39ae93e3a3
commit
67b563f1f2
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@ -13,6 +13,7 @@ if SPMI
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config SPMI_MSM_PMIC_ARB
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tristate "Qualcomm MSM SPMI Controller (PMIC Arbiter)"
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depends on ARM
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depends on IRQ_DOMAIN
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depends on ARCH_MSM || COMPILE_TEST
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default ARCH_MSM
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help
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@ -13,6 +13,9 @@
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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@ -103,6 +106,14 @@ enum pmic_arb_cmd_op_code {
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* @cnfg: address of the PMIC Arbiter configuration registers.
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* @lock: lock to synchronize accesses.
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* @channel: which channel to use for accesses.
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* @irq: PMIC ARB interrupt.
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* @ee: the current Execution Environment
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* @min_apid: minimum APID (used for bounding IRQ search)
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* @max_apid: maximum APID
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* @mapping_table: in-memory copy of PPID -> APID mapping table.
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* @domain: irq domain object for PMIC IRQ domain
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* @spmic: SPMI controller object
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* @apid_to_ppid: cached mapping from APID to PPID
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*/
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struct spmi_pmic_arb_dev {
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void __iomem *base;
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@ -110,6 +121,14 @@ struct spmi_pmic_arb_dev {
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void __iomem *cnfg;
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raw_spinlock_t lock;
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u8 channel;
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int irq;
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u8 ee;
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u8 min_apid;
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u8 max_apid;
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u32 mapping_table[SPMI_MAPPING_TABLE_LEN];
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struct irq_domain *domain;
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struct spmi_controller *spmic;
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u16 apid_to_ppid[256];
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};
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static inline u32 pmic_arb_base_read(struct spmi_pmic_arb_dev *dev, u32 offset)
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@ -306,12 +325,316 @@ static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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return rc;
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}
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enum qpnpint_regs {
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QPNPINT_REG_RT_STS = 0x10,
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QPNPINT_REG_SET_TYPE = 0x11,
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QPNPINT_REG_POLARITY_HIGH = 0x12,
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QPNPINT_REG_POLARITY_LOW = 0x13,
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QPNPINT_REG_LATCHED_CLR = 0x14,
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QPNPINT_REG_EN_SET = 0x15,
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QPNPINT_REG_EN_CLR = 0x16,
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QPNPINT_REG_LATCHED_STS = 0x18,
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};
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struct spmi_pmic_arb_qpnpint_type {
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u8 type; /* 1 -> edge */
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u8 polarity_high;
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u8 polarity_low;
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} __packed;
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/* Simplified accessor functions for irqchip callbacks */
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static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
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size_t len)
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{
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struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
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u8 sid = d->hwirq >> 24;
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u8 per = d->hwirq >> 16;
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if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid,
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(per << 8) + reg, buf, len))
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dev_err_ratelimited(&pa->spmic->dev,
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"failed irqchip transaction on %x\n",
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d->irq);
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}
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static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
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{
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struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
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u8 sid = d->hwirq >> 24;
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u8 per = d->hwirq >> 16;
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if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid,
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(per << 8) + reg, buf, len))
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dev_err_ratelimited(&pa->spmic->dev,
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"failed irqchip transaction on %x\n",
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d->irq);
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}
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static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid)
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{
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unsigned int irq;
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u32 status;
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int id;
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status = readl_relaxed(pa->intr + SPMI_PIC_IRQ_STATUS(apid));
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while (status) {
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id = ffs(status) - 1;
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status &= ~(1 << id);
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irq = irq_find_mapping(pa->domain,
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pa->apid_to_ppid[apid] << 16
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| id << 8
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| apid);
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generic_handle_irq(irq);
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}
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}
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static void pmic_arb_chained_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct spmi_pmic_arb_dev *pa = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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void __iomem *intr = pa->intr;
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int first = pa->min_apid >> 5;
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int last = pa->max_apid >> 5;
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u32 status;
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int i, id;
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chained_irq_enter(chip, desc);
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for (i = first; i <= last; ++i) {
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status = readl_relaxed(intr +
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SPMI_PIC_OWNER_ACC_STATUS(pa->ee, i));
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while (status) {
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id = ffs(status) - 1;
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status &= ~(1 << id);
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periph_interrupt(pa, id + i * 32);
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}
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}
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chained_irq_exit(chip, desc);
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}
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static void qpnpint_irq_ack(struct irq_data *d)
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{
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struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
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u8 irq = d->hwirq >> 8;
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u8 apid = d->hwirq;
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unsigned long flags;
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u8 data;
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raw_spin_lock_irqsave(&pa->lock, flags);
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writel_relaxed(1 << irq, pa->intr + SPMI_PIC_IRQ_CLEAR(apid));
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raw_spin_unlock_irqrestore(&pa->lock, flags);
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data = 1 << irq;
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qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
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}
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static void qpnpint_irq_mask(struct irq_data *d)
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{
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struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
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u8 irq = d->hwirq >> 8;
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u8 apid = d->hwirq;
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unsigned long flags;
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u32 status;
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u8 data;
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raw_spin_lock_irqsave(&pa->lock, flags);
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status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
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if (status & SPMI_PIC_ACC_ENABLE_BIT) {
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status = status & ~SPMI_PIC_ACC_ENABLE_BIT;
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writel_relaxed(status, pa->intr + SPMI_PIC_ACC_ENABLE(apid));
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}
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raw_spin_unlock_irqrestore(&pa->lock, flags);
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data = 1 << irq;
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qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
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}
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static void qpnpint_irq_unmask(struct irq_data *d)
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{
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struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
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u8 irq = d->hwirq >> 8;
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u8 apid = d->hwirq;
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unsigned long flags;
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u32 status;
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u8 data;
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raw_spin_lock_irqsave(&pa->lock, flags);
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status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
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if (!(status & SPMI_PIC_ACC_ENABLE_BIT)) {
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writel_relaxed(status | SPMI_PIC_ACC_ENABLE_BIT,
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pa->intr + SPMI_PIC_ACC_ENABLE(apid));
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}
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raw_spin_unlock_irqrestore(&pa->lock, flags);
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data = 1 << irq;
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qpnpint_spmi_write(d, QPNPINT_REG_EN_SET, &data, 1);
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}
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static void qpnpint_irq_enable(struct irq_data *d)
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{
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u8 irq = d->hwirq >> 8;
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u8 data;
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qpnpint_irq_unmask(d);
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data = 1 << irq;
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qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
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}
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static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct spmi_pmic_arb_qpnpint_type type;
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u8 irq = d->hwirq >> 8;
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qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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type.type |= 1 << irq;
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if (flow_type & IRQF_TRIGGER_RISING)
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type.polarity_high |= 1 << irq;
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if (flow_type & IRQF_TRIGGER_FALLING)
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type.polarity_low |= 1 << irq;
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} else {
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if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
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(flow_type & (IRQF_TRIGGER_LOW)))
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return -EINVAL;
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type.type &= ~(1 << irq); /* level trig */
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if (flow_type & IRQF_TRIGGER_HIGH)
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type.polarity_high |= 1 << irq;
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else
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type.polarity_low |= 1 << irq;
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}
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qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
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return 0;
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}
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static struct irq_chip pmic_arb_irqchip = {
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.name = "pmic_arb",
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.irq_enable = qpnpint_irq_enable,
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.irq_ack = qpnpint_irq_ack,
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.irq_mask = qpnpint_irq_mask,
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.irq_unmask = qpnpint_irq_unmask,
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.irq_set_type = qpnpint_irq_set_type,
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.flags = IRQCHIP_MASK_ON_SUSPEND
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| IRQCHIP_SKIP_SET_WAKE,
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};
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struct spmi_pmic_arb_irq_spec {
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unsigned slave:4;
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unsigned per:8;
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unsigned irq:3;
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};
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static int search_mapping_table(struct spmi_pmic_arb_dev *pa,
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struct spmi_pmic_arb_irq_spec *spec,
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u8 *apid)
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{
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u16 ppid = spec->slave << 8 | spec->per;
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u32 *mapping_table = pa->mapping_table;
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int index = 0, i;
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u32 data;
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for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
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data = mapping_table[index];
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if (ppid & (1 << SPMI_MAPPING_BIT_INDEX(data))) {
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if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
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index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
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} else {
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*apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
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return 0;
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}
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} else {
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if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
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index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
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} else {
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*apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
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return 0;
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}
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}
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}
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return -ENODEV;
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}
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static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec,
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unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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struct spmi_pmic_arb_dev *pa = d->host_data;
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struct spmi_pmic_arb_irq_spec spec;
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int err;
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u8 apid;
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dev_dbg(&pa->spmic->dev,
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"intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
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intspec[0], intspec[1], intspec[2]);
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if (d->of_node != controller)
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return -EINVAL;
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if (intsize != 4)
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return -EINVAL;
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if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
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return -EINVAL;
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spec.slave = intspec[0];
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spec.per = intspec[1];
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spec.irq = intspec[2];
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err = search_mapping_table(pa, &spec, &apid);
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if (err)
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return err;
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pa->apid_to_ppid[apid] = spec.slave << 8 | spec.per;
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/* Keep track of {max,min}_apid for bounding search during interrupt */
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if (apid > pa->max_apid)
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pa->max_apid = apid;
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if (apid < pa->min_apid)
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pa->min_apid = apid;
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*out_hwirq = spec.slave << 24
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| spec.per << 16
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| spec.irq << 8
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| apid;
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*out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
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dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
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return 0;
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}
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static int qpnpint_irq_domain_map(struct irq_domain *d,
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unsigned int virq,
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irq_hw_number_t hwirq)
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{
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struct spmi_pmic_arb_dev *pa = d->host_data;
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dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq);
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irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq);
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irq_set_chip_data(virq, d->host_data);
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irq_set_noprobe(virq);
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return 0;
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}
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static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
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.map = qpnpint_irq_domain_map,
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.xlate = qpnpint_irq_domain_dt_translate,
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};
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static int spmi_pmic_arb_probe(struct platform_device *pdev)
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{
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struct spmi_pmic_arb_dev *pa;
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struct spmi_controller *ctrl;
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struct resource *res;
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u32 channel;
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u32 channel, ee;
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int err, i;
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ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa));
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@ -319,6 +642,7 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
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return -ENOMEM;
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pa = spmi_controller_get_drvdata(ctrl);
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pa->spmic = ctrl;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
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pa->base = devm_ioremap_resource(&ctrl->dev, res);
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@ -341,6 +665,12 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
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goto err_put_ctrl;
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}
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pa->irq = platform_get_irq_byname(pdev, "periph_irq");
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if (pa->irq < 0) {
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err = pa->irq;
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goto err_put_ctrl;
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}
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err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
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if (err) {
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dev_err(&pdev->dev, "channel unspecified.\n");
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@ -355,6 +685,29 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
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pa->channel = channel;
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err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
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if (err) {
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dev_err(&pdev->dev, "EE unspecified.\n");
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goto err_put_ctrl;
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}
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if (ee > 5) {
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dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
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err = -EINVAL;
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goto err_put_ctrl;
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}
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pa->ee = ee;
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for (i = 0; i < ARRAY_SIZE(pa->mapping_table); ++i)
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pa->mapping_table[i] = readl_relaxed(
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pa->cnfg + SPMI_MAPPING_TABLE_REG(i));
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/* Initialize max_apid/min_apid to the opposite bounds, during
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* the irq domain translation, we are sure to update these */
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pa->max_apid = 0;
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pa->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
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platform_set_drvdata(pdev, ctrl);
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raw_spin_lock_init(&pa->lock);
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@ -362,15 +715,31 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
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ctrl->read_cmd = pmic_arb_read_cmd;
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ctrl->write_cmd = pmic_arb_write_cmd;
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dev_dbg(&pdev->dev, "adding irq domain\n");
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pa->domain = irq_domain_add_tree(pdev->dev.of_node,
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&pmic_arb_irq_domain_ops, pa);
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if (!pa->domain) {
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dev_err(&pdev->dev, "unable to create irq_domain\n");
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err = -ENOMEM;
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goto err_put_ctrl;
|
||||
}
|
||||
|
||||
irq_set_handler_data(pa->irq, pa);
|
||||
irq_set_chained_handler(pa->irq, pmic_arb_chained_irq);
|
||||
|
||||
err = spmi_controller_add(ctrl);
|
||||
if (err)
|
||||
goto err_put_ctrl;
|
||||
goto err_domain_remove;
|
||||
|
||||
dev_dbg(&ctrl->dev, "PMIC Arb Version 0x%x\n",
|
||||
pmic_arb_base_read(pa, PMIC_ARB_VERSION));
|
||||
|
||||
return 0;
|
||||
|
||||
err_domain_remove:
|
||||
irq_set_chained_handler(pa->irq, NULL);
|
||||
irq_set_handler_data(pa->irq, NULL);
|
||||
irq_domain_remove(pa->domain);
|
||||
err_put_ctrl:
|
||||
spmi_controller_put(ctrl);
|
||||
return err;
|
||||
|
|
@ -379,7 +748,11 @@ err_put_ctrl:
|
|||
static int spmi_pmic_arb_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spmi_controller *ctrl = platform_get_drvdata(pdev);
|
||||
struct spmi_pmic_arb_dev *pa = spmi_controller_get_drvdata(ctrl);
|
||||
spmi_controller_remove(ctrl);
|
||||
irq_set_chained_handler(pa->irq, NULL);
|
||||
irq_set_handler_data(pa->irq, NULL);
|
||||
irq_domain_remove(pa->domain);
|
||||
spmi_controller_put(ctrl);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue