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mfd: sec-irq: Use consistent S2MPS11 RTC alarm interrupt indexes 

The S2MPS11 RTC has two alarms: alarm0 and alarm1 (corresponding
interrupts are named similarly). Use consistent names for interrupts to
limit possible errors.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Krzysztof Kozlowski 2014-02-28 11:41:43 +01:00 committed by Lee Jones
parent 3e5a45f7f1
commit 677620952a
2 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/mfd/sec-irq.c
View File

@ -59,14 +59,14 @@ static const struct regmap_irq s2mps11_irqs[] = {
.reg_offset = 1, .reg_offset = 1,
.mask = S2MPS11_IRQ_RTC60S_MASK, .mask = S2MPS11_IRQ_RTC60S_MASK,
}, },
[S2MPS11_IRQ_RTCA0] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA0_MASK,
},
[S2MPS11_IRQ_RTCA1] = { [S2MPS11_IRQ_RTCA1] = {
.reg_offset = 1, .reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA1_MASK, .mask = S2MPS11_IRQ_RTCA1_MASK,
}, },
[S2MPS11_IRQ_RTCA2] = {
.reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA2_MASK,
},
[S2MPS11_IRQ_SMPL] = { [S2MPS11_IRQ_SMPL] = {
.reg_offset = 1, .reg_offset = 1,
.mask = S2MPS11_IRQ_SMPL_MASK, .mask = S2MPS11_IRQ_SMPL_MASK,

4
include/linux/mfd/samsung/irq.h
View File

@ -24,8 +24,8 @@ enum s2mps11_irq {
S2MPS11_IRQ_MRB, S2MPS11_IRQ_MRB,
S2MPS11_IRQ_RTC60S, S2MPS11_IRQ_RTC60S,
S2MPS11_IRQ_RTCA0,
S2MPS11_IRQ_RTCA1, S2MPS11_IRQ_RTCA1,
S2MPS11_IRQ_RTCA2,
S2MPS11_IRQ_SMPL, S2MPS11_IRQ_SMPL,
S2MPS11_IRQ_RTC1S, S2MPS11_IRQ_RTC1S,
S2MPS11_IRQ_WTSR, S2MPS11_IRQ_WTSR,
@ -47,7 +47,7 @@ enum s2mps11_irq {
#define S2MPS11_IRQ_RTC60S_MASK (1 << 0) #define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
#define S2MPS11_IRQ_RTCA1_MASK (1 << 1) #define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
#define S2MPS11_IRQ_RTCA2_MASK (1 << 2) #define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
#define S2MPS11_IRQ_SMPL_MASK (1 << 3) #define S2MPS11_IRQ_SMPL_MASK (1 << 3)
#define S2MPS11_IRQ_RTC1S_MASK (1 << 4) #define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
#define S2MPS11_IRQ_WTSR_MASK (1 << 5) #define S2MPS11_IRQ_WTSR_MASK (1 << 5)