mfd: sec-irq: Use consistent S2MPS11 RTC alarm interrupt indexes
The S2MPS11 RTC has two alarms: alarm0 and alarm1 (corresponding interrupts are named similarly). Use consistent names for interrupts to limit possible errors. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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@ -59,14 +59,14 @@ static const struct regmap_irq s2mps11_irqs[] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTC60S_MASK,
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},
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[S2MPS11_IRQ_RTCA0] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTCA0_MASK,
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},
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[S2MPS11_IRQ_RTCA1] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTCA1_MASK,
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},
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[S2MPS11_IRQ_RTCA2] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_RTCA2_MASK,
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},
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[S2MPS11_IRQ_SMPL] = {
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.reg_offset = 1,
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.mask = S2MPS11_IRQ_SMPL_MASK,
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@ -24,8 +24,8 @@ enum s2mps11_irq {
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S2MPS11_IRQ_MRB,
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S2MPS11_IRQ_RTC60S,
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S2MPS11_IRQ_RTCA0,
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S2MPS11_IRQ_RTCA1,
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S2MPS11_IRQ_RTCA2,
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S2MPS11_IRQ_SMPL,
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S2MPS11_IRQ_RTC1S,
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S2MPS11_IRQ_WTSR,
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@ -47,7 +47,7 @@ enum s2mps11_irq {
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#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPS11_IRQ_RTCA2_MASK (1 << 2)
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#define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
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#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
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