spi: spi-fsl-dspi: Fix little endian access to PUSHR CMD and TXDATA
In XSPI mode, the 32-bit PUSHR register can be written to separately:
the higher 16 bits are for commands and the lower 16 bits are for data.
This has nicely been hacked around, by defining a second regmap with a
width of 16 bits, and effectively splitting a 32-bit register into 2
16-bit ones, from the perspective of this regmap_pushr.
The problem is the assumption about the controller's endianness. If the
controller is little endian (such as anything post-LS1046A), then the
first 2 bytes, in the order imposed by memory layout, will actually hold
the TXDATA, and the last 2 bytes will hold the CMD.
So take the controller's endianness into account when performing split
writes to PUSHR. The obvious and simple solution would have been to call
regmap_get_val_endian(), but that is an internal regmap function and we
don't want to change regmap just for this. Therefore, we just re-read
the "big-endian" device tree property.
Fixes: 58ba07ec79
("spi: spi-fsl-dspi: Add support for XSPI mode registers")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20200318001603.9650-3-olteanv@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
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4fcc7c2292
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671ffde175
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@ -103,10 +103,6 @@
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#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
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#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
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/* Register offsets for regmap_pushr */
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#define PUSHR_CMD 0x0
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#define PUSHR_TX 0x2
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#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
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struct chip_data {
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@ -240,6 +236,13 @@ struct fsl_dspi {
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int words_in_flight;
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/*
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* Offsets for CMD and TXDATA within SPI_PUSHR when accessed
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* individually (in XSPI mode)
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*/
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int pushr_cmd;
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int pushr_tx;
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void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
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void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
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};
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@ -673,12 +676,12 @@ static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)
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*/
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if (dspi->len > dspi->oper_word_size)
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cmd |= SPI_PUSHR_CMD_CONT;
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regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd);
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regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd);
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}
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static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata)
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{
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regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata);
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regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata);
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}
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static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt, bool eoq)
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@ -1259,6 +1262,7 @@ static int dspi_probe(struct platform_device *pdev)
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struct fsl_dspi *dspi;
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struct resource *res;
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void __iomem *base;
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bool big_endian;
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ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
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if (!ctlr)
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@ -1284,6 +1288,7 @@ static int dspi_probe(struct platform_device *pdev)
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/* Only Coldfire uses platform data */
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dspi->devtype_data = &devtype_data[MCF5441X];
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big_endian = true;
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} else {
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ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
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@ -1305,6 +1310,15 @@ static int dspi_probe(struct platform_device *pdev)
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ret = -EFAULT;
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goto out_ctlr_put;
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}
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big_endian = of_device_is_big_endian(np);
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}
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if (big_endian) {
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dspi->pushr_cmd = 0;
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dspi->pushr_tx = 2;
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} else {
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dspi->pushr_cmd = 2;
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dspi->pushr_tx = 0;
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}
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if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
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