[ARM] 3430/1: ARM: OMAP: 5/8 Update PM
Patch from Tony Lindgren Update OMAP PM code from linux-omap tree: - Move PM code from plat-omap to mach-omap1 and mach-omap2 by Tony Lindgren - Add minimal PM support for omap24xx by Tony Lindgren and Richard Woodruff - Misc updates to omap1 PM code by Tuukka Tikkanen et al - Updates to the SRAM code needed for PM and FB by Imre Deak Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Tony Lindgren
Russell King
parent
6e60e79a1d
commit
670c104ae8
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@ -0,0 +1,770 @@
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/*
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* linux/arch/arm/mach-omap1/pm.c
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*
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* OMAP Power Management Routines
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*
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* Original code for the SA11x0:
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* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
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*
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* Modified for the PXA250 by Nicolas Pitre:
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* Copyright (c) 2002 Monta Vista Software, Inc.
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*
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* Modified for the OMAP1510 by David Singleton:
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* Copyright (c) 2002 Monta Vista Software, Inc.
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*
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* Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/pm.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/pm.h>
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#include <linux/interrupt.h>
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#include <linux/sysfs.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/atomic.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/mach-types.h>
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#include <asm/arch/irqs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sram.h>
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#include <asm/arch/tc.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/tps65010.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/dsp_common.h>
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#include <asm/arch/dmtimer.h>
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static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
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static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
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static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
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static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
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static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
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static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
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static unsigned short enable_dyn_sleep = 1;
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static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf)
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{
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return sprintf(buf, "%hu\n", enable_dyn_sleep);
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}
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static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys,
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const char * buf,
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size_t n)
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{
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unsigned short value;
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if (sscanf(buf, "%hu", &value) != 1 ||
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(value != 0 && value != 1)) {
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printk(KERN_ERR "idle_sleep_store: Invalid value\n");
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return -EINVAL;
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}
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enable_dyn_sleep = value;
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return n;
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}
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static struct subsys_attribute sleep_while_idle_attr = {
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.attr = {
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.name = __stringify(sleep_while_idle),
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.mode = 0644,
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},
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.show = omap_pm_sleep_while_idle_show,
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.store = omap_pm_sleep_while_idle_store,
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};
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extern struct subsystem power_subsys;
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static void (*omap_sram_idle)(void) = NULL;
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static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
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/*
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* Let's power down on idle, but only if we are really
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* idle, because once we start down the path of
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* going idle we continue to do idle even if we get
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* a clock tick interrupt . .
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*/
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void omap_pm_idle(void)
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{
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extern __u32 arm_idlect1_mask;
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__u32 use_idlect1 = arm_idlect1_mask;
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#ifndef CONFIG_OMAP_MPU_TIMER
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int do_sleep;
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#endif
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local_irq_disable();
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local_fiq_disable();
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if (need_resched()) {
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local_fiq_enable();
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local_irq_enable();
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return;
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}
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/*
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* Since an interrupt may set up a timer, we don't want to
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* reprogram the hardware timer with interrupts enabled.
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* Re-enable interrupts only after returning from idle.
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*/
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timer_dyn_reprogram();
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#ifdef CONFIG_OMAP_MPU_TIMER
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#warning Enable 32kHz OS timer in order to allow sleep states in idle
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use_idlect1 = use_idlect1 & ~(1 << 9);
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#else
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do_sleep = 0;
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while (enable_dyn_sleep) {
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#ifdef CONFIG_CBUS_TAHVO_USB
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extern int vbus_active;
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/* Clock requirements? */
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if (vbus_active)
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break;
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#endif
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do_sleep = 1;
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break;
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}
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#ifdef CONFIG_OMAP_DM_TIMER
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use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
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#endif
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if (omap_dma_running()) {
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use_idlect1 &= ~(1 << 6);
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if (omap_lcd_dma_ext_running())
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use_idlect1 &= ~(1 << 12);
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}
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/* We should be able to remove the do_sleep variable and multiple
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* tests above as soon as drivers, timer and DMA code have been fixed.
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* Even the sleep block count should become obsolete. */
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if ((use_idlect1 != ~0) || !do_sleep) {
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__u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
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if (cpu_is_omap15xx())
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use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
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else
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use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
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omap_writel(use_idlect1, ARM_IDLECT1);
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__asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
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omap_writel(saved_idlect1, ARM_IDLECT1);
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local_fiq_enable();
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local_irq_enable();
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return;
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}
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omap_sram_suspend(omap_readl(ARM_IDLECT1),
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omap_readl(ARM_IDLECT2));
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#endif
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local_fiq_enable();
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local_irq_enable();
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}
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/*
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* Configuration of the wakeup event is board specific. For the
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* moment we put it into this helper function. Later it may move
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* to board specific files.
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*/
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static void omap_pm_wakeup_setup(void)
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{
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u32 level1_wake = 0;
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u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
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/*
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* Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
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* and the L2 wakeup interrupts: keypad and UART2. Note that the
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* drivers must still separately call omap_set_gpio_wakeup() to
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* wake up to a GPIO interrupt.
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*/
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if (cpu_is_omap730())
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level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
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OMAP_IRQ_BIT(INT_730_IH2_IRQ);
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else if (cpu_is_omap15xx())
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level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
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OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
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else if (cpu_is_omap16xx())
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level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
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OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
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omap_writel(~level1_wake, OMAP_IH1_MIR);
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if (cpu_is_omap730()) {
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omap_writel(~level2_wake, OMAP_IH2_0_MIR);
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omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
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OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
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OMAP_IH2_1_MIR);
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} else if (cpu_is_omap15xx()) {
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level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
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omap_writel(~level2_wake, OMAP_IH2_MIR);
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} else if (cpu_is_omap16xx()) {
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level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
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omap_writel(~level2_wake, OMAP_IH2_0_MIR);
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/* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
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omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
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OMAP_IH2_1_MIR);
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omap_writel(~0x0, OMAP_IH2_2_MIR);
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omap_writel(~0x0, OMAP_IH2_3_MIR);
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}
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/* New IRQ agreement, recalculate in cascade order */
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omap_writel(1, OMAP_IH2_CONTROL);
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omap_writel(1, OMAP_IH1_CONTROL);
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}
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#define EN_DSPCK 13 /* ARM_CKCTL */
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#define EN_APICK 6 /* ARM_IDLECT2 */
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#define DSP_EN 1 /* ARM_RSTCT1 */
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void omap_pm_suspend(void)
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{
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unsigned long arg0 = 0, arg1 = 0;
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printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
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omap_serial_wake_trigger(1);
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if (machine_is_omap_osk()) {
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/* Stop LED1 (D9) blink */
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tps65010_set_led(LED1, OFF);
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}
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omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
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/*
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* Step 1: turn off interrupts (FIXME: NOTE: already disabled)
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*/
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local_irq_disable();
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local_fiq_disable();
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/*
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* Step 2: save registers
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*
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* The omap is a strange/beautiful device. The caches, memory
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* and register state are preserved across power saves.
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* We have to save and restore very little register state to
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* idle the omap.
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*
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* Save interrupt, MPUI, ARM and UPLD control registers.
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*/
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if (cpu_is_omap730()) {
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MPUI730_SAVE(OMAP_IH1_MIR);
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MPUI730_SAVE(OMAP_IH2_0_MIR);
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MPUI730_SAVE(OMAP_IH2_1_MIR);
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MPUI730_SAVE(MPUI_CTRL);
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MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
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MPUI730_SAVE(MPUI_DSP_API_CONFIG);
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MPUI730_SAVE(EMIFS_CONFIG);
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MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
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} else if (cpu_is_omap15xx()) {
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MPUI1510_SAVE(OMAP_IH1_MIR);
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MPUI1510_SAVE(OMAP_IH2_MIR);
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MPUI1510_SAVE(MPUI_CTRL);
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MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
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MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
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MPUI1510_SAVE(EMIFS_CONFIG);
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MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
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} else if (cpu_is_omap16xx()) {
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MPUI1610_SAVE(OMAP_IH1_MIR);
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MPUI1610_SAVE(OMAP_IH2_0_MIR);
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MPUI1610_SAVE(OMAP_IH2_1_MIR);
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MPUI1610_SAVE(OMAP_IH2_2_MIR);
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MPUI1610_SAVE(OMAP_IH2_3_MIR);
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MPUI1610_SAVE(MPUI_CTRL);
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MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
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MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
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MPUI1610_SAVE(EMIFS_CONFIG);
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MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
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}
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ARM_SAVE(ARM_CKCTL);
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ARM_SAVE(ARM_IDLECT1);
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ARM_SAVE(ARM_IDLECT2);
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if (!(cpu_is_omap15xx()))
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ARM_SAVE(ARM_IDLECT3);
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ARM_SAVE(ARM_EWUPCT);
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ARM_SAVE(ARM_RSTCT1);
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ARM_SAVE(ARM_RSTCT2);
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ARM_SAVE(ARM_SYSST);
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ULPD_SAVE(ULPD_CLOCK_CTRL);
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ULPD_SAVE(ULPD_STATUS_REQ);
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/* (Step 3 removed - we now allow deep sleep by default) */
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/*
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* Step 4: OMAP DSP Shutdown
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*/
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/* stop DSP */
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omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
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/* shut down dsp_ck */
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omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
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/* temporarily enabling api_ck to access DSP registers */
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omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
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/* save DSP registers */
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DSP_SAVE(DSP_IDLECT2);
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/* Stop all DSP domain clocks */
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__raw_writew(0, DSP_IDLECT2);
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/*
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* Step 5: Wakeup Event Setup
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*/
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omap_pm_wakeup_setup();
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/*
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* Step 6: ARM and Traffic controller shutdown
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*/
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/* disable ARM watchdog */
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omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
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omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
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/*
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* Step 6b: ARM and Traffic controller shutdown
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*
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* Step 6 continues here. Prepare jump to power management
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* assembly code in internal SRAM.
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*
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* Since the omap_cpu_suspend routine has been copied to
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* SRAM, we'll do an indirect procedure call to it and pass the
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* contents of arm_idlect1 and arm_idlect2 so it can restore
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* them when it wakes up and it will return.
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*/
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arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
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arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
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/*
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* Step 6c: ARM and Traffic controller shutdown
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*
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* Jump to assembly code. The processor will stay there
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* until wake up.
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*/
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omap_sram_suspend(arg0, arg1);
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/*
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* If we are here, processor is woken up!
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*/
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/*
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* Restore DSP clocks
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*/
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/* again temporarily enabling api_ck to access DSP registers */
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omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
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/* Restore DSP domain clocks */
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DSP_RESTORE(DSP_IDLECT2);
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/*
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* Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
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*/
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if (!(cpu_is_omap15xx()))
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ARM_RESTORE(ARM_IDLECT3);
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ARM_RESTORE(ARM_CKCTL);
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ARM_RESTORE(ARM_EWUPCT);
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ARM_RESTORE(ARM_RSTCT1);
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ARM_RESTORE(ARM_RSTCT2);
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ARM_RESTORE(ARM_SYSST);
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ULPD_RESTORE(ULPD_CLOCK_CTRL);
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ULPD_RESTORE(ULPD_STATUS_REQ);
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if (cpu_is_omap730()) {
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MPUI730_RESTORE(EMIFS_CONFIG);
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MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
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MPUI730_RESTORE(OMAP_IH1_MIR);
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MPUI730_RESTORE(OMAP_IH2_0_MIR);
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MPUI730_RESTORE(OMAP_IH2_1_MIR);
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} else if (cpu_is_omap15xx()) {
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MPUI1510_RESTORE(MPUI_CTRL);
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MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
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MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
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MPUI1510_RESTORE(EMIFS_CONFIG);
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MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
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MPUI1510_RESTORE(OMAP_IH1_MIR);
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MPUI1510_RESTORE(OMAP_IH2_MIR);
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} else if (cpu_is_omap16xx()) {
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MPUI1610_RESTORE(MPUI_CTRL);
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MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
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MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
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MPUI1610_RESTORE(EMIFS_CONFIG);
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MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
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MPUI1610_RESTORE(OMAP_IH1_MIR);
|
||||
MPUI1610_RESTORE(OMAP_IH2_0_MIR);
|
||||
MPUI1610_RESTORE(OMAP_IH2_1_MIR);
|
||||
MPUI1610_RESTORE(OMAP_IH2_2_MIR);
|
||||
MPUI1610_RESTORE(OMAP_IH2_3_MIR);
|
||||
}
|
||||
|
||||
omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
|
||||
|
||||
/*
|
||||
* Reenable interrupts
|
||||
*/
|
||||
|
||||
local_irq_enable();
|
||||
local_fiq_enable();
|
||||
|
||||
omap_serial_wake_trigger(0);
|
||||
|
||||
printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
|
||||
|
||||
if (machine_is_omap_osk()) {
|
||||
/* Let LED1 (D9) blink again */
|
||||
tps65010_set_led(LED1, BLINK);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(DEBUG) && defined(CONFIG_PROC_FS)
|
||||
static int g_read_completed;
|
||||
|
||||
/*
|
||||
* Read system PM registers for debugging
|
||||
*/
|
||||
static int omap_pm_read_proc(
|
||||
char *page_buffer,
|
||||
char **my_first_byte,
|
||||
off_t virtual_start,
|
||||
int length,
|
||||
int *eof,
|
||||
void *data)
|
||||
{
|
||||
int my_buffer_offset = 0;
|
||||
char * const my_base = page_buffer;
|
||||
|
||||
ARM_SAVE(ARM_CKCTL);
|
||||
ARM_SAVE(ARM_IDLECT1);
|
||||
ARM_SAVE(ARM_IDLECT2);
|
||||
if (!(cpu_is_omap15xx()))
|
||||
ARM_SAVE(ARM_IDLECT3);
|
||||
ARM_SAVE(ARM_EWUPCT);
|
||||
ARM_SAVE(ARM_RSTCT1);
|
||||
ARM_SAVE(ARM_RSTCT2);
|
||||
ARM_SAVE(ARM_SYSST);
|
||||
|
||||
ULPD_SAVE(ULPD_IT_STATUS);
|
||||
ULPD_SAVE(ULPD_CLOCK_CTRL);
|
||||
ULPD_SAVE(ULPD_SOFT_REQ);
|
||||
ULPD_SAVE(ULPD_STATUS_REQ);
|
||||
ULPD_SAVE(ULPD_DPLL_CTRL);
|
||||
ULPD_SAVE(ULPD_POWER_CTRL);
|
||||
|
||||
if (cpu_is_omap730()) {
|
||||
MPUI730_SAVE(MPUI_CTRL);
|
||||
MPUI730_SAVE(MPUI_DSP_STATUS);
|
||||
MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
|
||||
MPUI730_SAVE(MPUI_DSP_API_CONFIG);
|
||||
MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
|
||||
MPUI730_SAVE(EMIFS_CONFIG);
|
||||
} else if (cpu_is_omap15xx()) {
|
||||
MPUI1510_SAVE(MPUI_CTRL);
|
||||
MPUI1510_SAVE(MPUI_DSP_STATUS);
|
||||
MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
|
||||
MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
|
||||
MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
|
||||
MPUI1510_SAVE(EMIFS_CONFIG);
|
||||
} else if (cpu_is_omap16xx()) {
|
||||
MPUI1610_SAVE(MPUI_CTRL);
|
||||
MPUI1610_SAVE(MPUI_DSP_STATUS);
|
||||
MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
|
||||
MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
|
||||
MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
|
||||
MPUI1610_SAVE(EMIFS_CONFIG);
|
||||
}
|
||||
|
||||
if (virtual_start == 0) {
|
||||
g_read_completed = 0;
|
||||
|
||||
my_buffer_offset += sprintf(my_base + my_buffer_offset,
|
||||
"ARM_CKCTL_REG: 0x%-8x \n"
|
||||
"ARM_IDLECT1_REG: 0x%-8x \n"
|
||||
"ARM_IDLECT2_REG: 0x%-8x \n"
|
||||
"ARM_IDLECT3_REG: 0x%-8x \n"
|
||||
"ARM_EWUPCT_REG: 0x%-8x \n"
|
||||
"ARM_RSTCT1_REG: 0x%-8x \n"
|
||||
"ARM_RSTCT2_REG: 0x%-8x \n"
|
||||
"ARM_SYSST_REG: 0x%-8x \n"
|
||||
"ULPD_IT_STATUS_REG: 0x%-4x \n"
|
||||
"ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
|
||||
"ULPD_SOFT_REQ_REG: 0x%-4x \n"
|
||||
"ULPD_DPLL_CTRL_REG: 0x%-4x \n"
|
||||
"ULPD_STATUS_REQ_REG: 0x%-4x \n"
|
||||
"ULPD_POWER_CTRL_REG: 0x%-4x \n",
|
||||
ARM_SHOW(ARM_CKCTL),
|
||||
ARM_SHOW(ARM_IDLECT1),
|
||||
ARM_SHOW(ARM_IDLECT2),
|
||||
ARM_SHOW(ARM_IDLECT3),
|
||||
ARM_SHOW(ARM_EWUPCT),
|
||||
ARM_SHOW(ARM_RSTCT1),
|
||||
ARM_SHOW(ARM_RSTCT2),
|
||||
ARM_SHOW(ARM_SYSST),
|
||||
ULPD_SHOW(ULPD_IT_STATUS),
|
||||
ULPD_SHOW(ULPD_CLOCK_CTRL),
|
||||
ULPD_SHOW(ULPD_SOFT_REQ),
|
||||
ULPD_SHOW(ULPD_DPLL_CTRL),
|
||||
ULPD_SHOW(ULPD_STATUS_REQ),
|
||||
ULPD_SHOW(ULPD_POWER_CTRL));
|
||||
|
||||
if (cpu_is_omap730()) {
|
||||
my_buffer_offset += sprintf(my_base + my_buffer_offset,
|
||||
"MPUI730_CTRL_REG 0x%-8x \n"
|
||||
"MPUI730_DSP_STATUS_REG: 0x%-8x \n"
|
||||
"MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
|
||||
MPUI730_SHOW(MPUI_CTRL),
|
||||
MPUI730_SHOW(MPUI_DSP_STATUS),
|
||||
MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
|
||||
MPUI730_SHOW(MPUI_DSP_API_CONFIG),
|
||||
MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
|
||||
MPUI730_SHOW(EMIFS_CONFIG));
|
||||
} else if (cpu_is_omap15xx()) {
|
||||
my_buffer_offset += sprintf(my_base + my_buffer_offset,
|
||||
"MPUI1510_CTRL_REG 0x%-8x \n"
|
||||
"MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
|
||||
"MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
|
||||
MPUI1510_SHOW(MPUI_CTRL),
|
||||
MPUI1510_SHOW(MPUI_DSP_STATUS),
|
||||
MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
|
||||
MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
|
||||
MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
|
||||
MPUI1510_SHOW(EMIFS_CONFIG));
|
||||
} else if (cpu_is_omap16xx()) {
|
||||
my_buffer_offset += sprintf(my_base + my_buffer_offset,
|
||||
"MPUI1610_CTRL_REG 0x%-8x \n"
|
||||
"MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
|
||||
"MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
|
||||
"MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
|
||||
MPUI1610_SHOW(MPUI_CTRL),
|
||||
MPUI1610_SHOW(MPUI_DSP_STATUS),
|
||||
MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
|
||||
MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
|
||||
MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
|
||||
MPUI1610_SHOW(EMIFS_CONFIG));
|
||||
}
|
||||
|
||||
g_read_completed++;
|
||||
} else if (g_read_completed >= 1) {
|
||||
*eof = 1;
|
||||
return 0;
|
||||
}
|
||||
g_read_completed++;
|
||||
|
||||
*my_first_byte = page_buffer;
|
||||
return my_buffer_offset;
|
||||
}
|
||||
|
||||
static void omap_pm_init_proc(void)
|
||||
{
|
||||
struct proc_dir_entry *entry;
|
||||
|
||||
entry = create_proc_read_entry("driver/omap_pm",
|
||||
S_IWUSR | S_IRUGO, NULL,
|
||||
omap_pm_read_proc, NULL);
|
||||
}
|
||||
|
||||
#endif /* DEBUG && CONFIG_PROC_FS */
|
||||
|
||||
static void (*saved_idle)(void) = NULL;
|
||||
|
||||
/*
|
||||
* omap_pm_prepare - Do preliminary suspend work.
|
||||
* @state: suspend state we're entering.
|
||||
*
|
||||
*/
|
||||
static int omap_pm_prepare(suspend_state_t state)
|
||||
{
|
||||
int error = 0;
|
||||
|
||||
/* We cannot sleep in idle until we have resumed */
|
||||
saved_idle = pm_idle;
|
||||
pm_idle = NULL;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
case PM_SUSPEND_STANDBY:
|
||||
case PM_SUSPEND_MEM:
|
||||
break;
|
||||
|
||||
case PM_SUSPEND_DISK:
|
||||
return -ENOTSUPP;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* omap_pm_enter - Actually enter a sleep state.
|
||||
* @state: State we're entering.
|
||||
*
|
||||
*/
|
||||
|
||||
static int omap_pm_enter(suspend_state_t state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case PM_SUSPEND_STANDBY:
|
||||
case PM_SUSPEND_MEM:
|
||||
omap_pm_suspend();
|
||||
break;
|
||||
|
||||
case PM_SUSPEND_DISK:
|
||||
return -ENOTSUPP;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* omap_pm_finish - Finish up suspend sequence.
|
||||
* @state: State we're coming out of.
|
||||
*
|
||||
* This is called after we wake back up (or if entering the sleep state
|
||||
* failed).
|
||||
*/
|
||||
|
||||
static int omap_pm_finish(suspend_state_t state)
|
||||
{
|
||||
pm_idle = saved_idle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static irqreturn_t omap_wakeup_interrupt(int irq, void * dev,
|
||||
struct pt_regs * regs)
|
||||
{
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction omap_wakeup_irq = {
|
||||
.name = "peripheral wakeup",
|
||||
.flags = SA_INTERRUPT,
|
||||
.handler = omap_wakeup_interrupt
|
||||
};
|
||||
|
||||
|
||||
|
||||
static struct pm_ops omap_pm_ops ={
|
||||
.pm_disk_mode = 0,
|
||||
.prepare = omap_pm_prepare,
|
||||
.enter = omap_pm_enter,
|
||||
.finish = omap_pm_finish,
|
||||
};
|
||||
|
||||
static int __init omap_pm_init(void)
|
||||
{
|
||||
printk("Power Management for TI OMAP.\n");
|
||||
|
||||
/*
|
||||
* We copy the assembler sleep/wakeup routines to SRAM.
|
||||
* These routines need to be in SRAM as that's the only
|
||||
* memory the MPU can see when it wakes up.
|
||||
*/
|
||||
if (cpu_is_omap730()) {
|
||||
omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
|
||||
omap730_idle_loop_suspend_sz);
|
||||
omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
|
||||
omap730_cpu_suspend_sz);
|
||||
} else if (cpu_is_omap15xx()) {
|
||||
omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
|
||||
omap1510_idle_loop_suspend_sz);
|
||||
omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
|
||||
omap1510_cpu_suspend_sz);
|
||||
} else if (cpu_is_omap16xx()) {
|
||||
omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
|
||||
omap1610_idle_loop_suspend_sz);
|
||||
omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
|
||||
omap1610_cpu_suspend_sz);
|
||||
}
|
||||
|
||||
if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
|
||||
printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pm_idle = omap_pm_idle;
|
||||
|
||||
if (cpu_is_omap730())
|
||||
setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
|
||||
else if (cpu_is_omap16xx())
|
||||
setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
|
||||
|
||||
/* Program new power ramp-up time
|
||||
* (0 for most boards since we don't lower voltage when in deep sleep)
|
||||
*/
|
||||
omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
|
||||
|
||||
/* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
|
||||
omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
|
||||
|
||||
/* Configure IDLECT3 */
|
||||
if (cpu_is_omap730())
|
||||
omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
|
||||
else if (cpu_is_omap16xx())
|
||||
omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
|
||||
|
||||
pm_set_ops(&omap_pm_ops);
|
||||
|
||||
#if defined(DEBUG) && defined(CONFIG_PROC_FS)
|
||||
omap_pm_init_proc();
|
||||
#endif
|
||||
|
||||
subsys_create_file(&power_subsys, &sleep_while_idle_attr);
|
||||
|
||||
if (cpu_is_omap16xx()) {
|
||||
/* configure LOW_PWR pin */
|
||||
omap_cfg_reg(T20_1610_LOW_PWR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
__initcall(omap_pm_init);
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/plat-omap/sleep.S
|
||||
* linux/arch/arm/mach-omap1/sleep.S
|
||||
*
|
||||
* Low-level OMAP730/1510/1610 sleep/wakeUp support
|
||||
*
|
||||
|
|
@ -383,60 +383,133 @@ ENTRY(omap1610_cpu_suspend)
|
|||
mcr p15, 0, r0, c7, c10, 4
|
||||
nop
|
||||
|
||||
@ load base address of Traffic Controller
|
||||
@ Load base address of Traffic Controller
|
||||
mov r6, #TCMIF_ASM_BASE & 0xff000000
|
||||
orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
|
||||
orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
|
||||
|
||||
@ prepare to put SDRAM into self-refresh manually
|
||||
@ Prepare to put SDRAM into self-refresh manually
|
||||
ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
|
||||
orr r9, r7, #SELF_REFRESH_MODE & 0xff000000
|
||||
orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff
|
||||
str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
|
||||
|
||||
@ prepare to put EMIFS to Sleep
|
||||
@ Prepare to put EMIFS to Sleep
|
||||
ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
|
||||
orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff
|
||||
str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
|
||||
|
||||
@ load base address of ARM_IDLECT1 and ARM_IDLECT2
|
||||
@ Load base address of ARM_IDLECT1 and ARM_IDLECT2
|
||||
mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
|
||||
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
|
||||
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
|
||||
|
||||
@ turn off clock domains
|
||||
@ do not disable PERCK (0x04)
|
||||
@ Turn off clock domains
|
||||
@ Do not disable PERCK (0x04)
|
||||
mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
|
||||
orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
|
||||
strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
|
||||
|
||||
@ request ARM idle
|
||||
@ Request ARM idle
|
||||
mov r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff
|
||||
orr r3, r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff00
|
||||
strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
|
||||
|
||||
@ disable instruction cache
|
||||
mrc p15, 0, r9, c1, c0, 0
|
||||
bic r2, r9, #0x1000
|
||||
mcr p15, 0, r2, c1, c0, 0
|
||||
nop
|
||||
|
||||
/*
|
||||
* Let's wait for the next wake up event to wake us up. r0 can't be
|
||||
* used here because r0 holds ARM_IDLECT1
|
||||
*/
|
||||
mov r2, #0
|
||||
mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
|
||||
|
||||
@ Errata (HEL3SU467, section 1.4.4) specifies nop-instructions
|
||||
@ according to this formula:
|
||||
@ 2 + (4*DPLL_MULT)/DPLL_DIV/ARMDIV
|
||||
@ Max DPLL_MULT = 18
|
||||
@ DPLL_DIV = 1
|
||||
@ ARMDIV = 1
|
||||
@ => 74 nop-instructions
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop @10
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop @20
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop @30
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop @40
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop @50
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop @60
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop @70
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop @74
|
||||
/*
|
||||
* omap1610_cpu_suspend()'s resume point.
|
||||
*
|
||||
* It will just start executing here, so we'll restore stuff from the
|
||||
* stack.
|
||||
*/
|
||||
@ re-enable Icache
|
||||
mcr p15, 0, r9, c1, c0, 0
|
||||
|
||||
@ reset the ARM_IDLECT1 and ARM_IDLECT2.
|
||||
@ Restore the ARM_IDLECT1 and ARM_IDLECT2.
|
||||
strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
|
||||
strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
|
||||
|
||||
|
|
@ -444,7 +517,7 @@ ENTRY(omap1610_cpu_suspend)
|
|||
str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
|
||||
str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
|
||||
|
||||
@ restore regs and return
|
||||
@ Restore regs and return
|
||||
ldmfd sp!, {r0 - r12, pc}
|
||||
|
||||
ENTRY(omap1610_cpu_suspend_sz)
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/pm.c
|
||||
*
|
||||
* OMAP2 Power Management Routines
|
||||
*
|
||||
* Copyright (C) 2006 Nokia Corporation
|
||||
* Tony Lindgren <tony@atomide.com>
|
||||
*
|
||||
* Copyright (C) 2005 Texas Instruments, Inc.
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* Based on pm.c for omap1
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/pm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/sysfs.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <asm/arch/irqs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sram.h>
|
||||
#include <asm/arch/pm.h>
|
||||
|
||||
static struct clk *vclk;
|
||||
static void (*omap2_sram_idle)(void);
|
||||
static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
|
||||
static void (*saved_idle)(void);
|
||||
|
||||
void omap2_pm_idle(void)
|
||||
{
|
||||
local_irq_disable();
|
||||
local_fiq_disable();
|
||||
if (need_resched()) {
|
||||
local_fiq_enable();
|
||||
local_irq_enable();
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Since an interrupt may set up a timer, we don't want to
|
||||
* reprogram the hardware timer with interrupts enabled.
|
||||
* Re-enable interrupts only after returning from idle.
|
||||
*/
|
||||
timer_dyn_reprogram();
|
||||
|
||||
omap2_sram_idle();
|
||||
local_fiq_enable();
|
||||
local_irq_enable();
|
||||
}
|
||||
|
||||
static int omap2_pm_prepare(suspend_state_t state)
|
||||
{
|
||||
int error = 0;
|
||||
|
||||
/* We cannot sleep in idle until we have resumed */
|
||||
saved_idle = pm_idle;
|
||||
pm_idle = NULL;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
case PM_SUSPEND_STANDBY:
|
||||
case PM_SUSPEND_MEM:
|
||||
break;
|
||||
|
||||
case PM_SUSPEND_DISK:
|
||||
return -ENOTSUPP;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
static int omap2_pm_enter(suspend_state_t state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case PM_SUSPEND_STANDBY:
|
||||
case PM_SUSPEND_MEM:
|
||||
/* FIXME: Add suspend */
|
||||
break;
|
||||
|
||||
case PM_SUSPEND_DISK:
|
||||
return -ENOTSUPP;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap2_pm_finish(suspend_state_t state)
|
||||
{
|
||||
pm_idle = saved_idle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pm_ops omap_pm_ops = {
|
||||
.pm_disk_mode = 0,
|
||||
.prepare = omap2_pm_prepare,
|
||||
.enter = omap2_pm_enter,
|
||||
.finish = omap2_pm_finish,
|
||||
};
|
||||
|
||||
int __init omap2_pm_init(void)
|
||||
{
|
||||
printk("Power Management for TI OMAP.\n");
|
||||
|
||||
vclk = clk_get(NULL, "virt_prcm_set");
|
||||
if (IS_ERR(vclk)) {
|
||||
printk(KERN_ERR "Could not get PM vclk\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/*
|
||||
* We copy the assembler sleep/wakeup routines to SRAM.
|
||||
* These routines need to be in SRAM as that's the only
|
||||
* memory the MPU can see when it wakes up.
|
||||
*/
|
||||
omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
|
||||
omap24xx_idle_loop_suspend_sz);
|
||||
|
||||
omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
|
||||
omap24xx_cpu_suspend_sz);
|
||||
|
||||
pm_set_ops(&omap_pm_ops);
|
||||
pm_idle = omap2_pm_idle;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
__initcall(omap2_pm_init);
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/sleep.S
|
||||
*
|
||||
* (C) Copyright 2004
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/arch/io.h>
|
||||
#include <asm/arch/pm.h>
|
||||
|
||||
#define A_32KSYNC_CR_V IO_ADDRESS(OMAP_TIMER32K_BASE+0x10)
|
||||
#define A_PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50)
|
||||
#define A_PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80)
|
||||
#define A_CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500)
|
||||
#define A_CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520)
|
||||
#define A_CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540)
|
||||
#define A_CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544)
|
||||
|
||||
#define A_SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60)
|
||||
#define A_SDRC_POWER_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70)
|
||||
#define A_SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4)
|
||||
#define A_SDRC0_V (0xC0000000)
|
||||
#define A_SDRC_MANUAL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8)
|
||||
|
||||
.text
|
||||
|
||||
/*
|
||||
* Forces OMAP into idle state
|
||||
*
|
||||
* omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
|
||||
* for normal idles.
|
||||
*
|
||||
* Note: This code get's copied to internal SRAM at boot. When the OMAP
|
||||
* wakes up it continues execution at the point it went to sleep.
|
||||
*/
|
||||
ENTRY(omap24xx_idle_loop_suspend)
|
||||
stmfd sp!, {r0, lr} @ save registers on stack
|
||||
mov r0, #0 @ clear for mcr setup
|
||||
mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
|
||||
ldmfd sp!, {r0, pc} @ restore regs and return
|
||||
|
||||
ENTRY(omap24xx_idle_loop_suspend_sz)
|
||||
.word . - omap24xx_idle_loop_suspend
|
||||
|
||||
/*
|
||||
* omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing
|
||||
* SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
|
||||
* SDRC.
|
||||
*
|
||||
* Input:
|
||||
* R0 : DLL ctrl value pre-Sleep
|
||||
* R1 : Processor+Revision
|
||||
* 2420: 0x21 = 242xES1, 0x26 = 242xES2.2
|
||||
* 2430: 0x31 = 2430ES1, 0x32 = 2430ES2
|
||||
*
|
||||
* The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
|
||||
* when we get called, but the DLL probably isn't. We will wait a bit more in
|
||||
* case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
|
||||
* if in unlocked mode.
|
||||
*
|
||||
* For less than 242x-ES2.2 upon wake from a sleep mode where the external
|
||||
* oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
|
||||
* clock can pass into the PRCM can cause problems at DSP and IVA.
|
||||
* To work around this the code will switch to the 32kHz source prior to sleep.
|
||||
* Post sleep we will shift back to using the DPLL. Apparently,
|
||||
* CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait
|
||||
* 3x12MHz + 3x32kHz clocks for a full switch.
|
||||
*
|
||||
* The DLL load value is not kept in RETENTION or OFF. It needs to be restored
|
||||
* at wake
|
||||
*/
|
||||
ENTRY(omap24xx_cpu_suspend)
|
||||
stmfd sp!, {r0 - r12, lr} @ save registers on stack
|
||||
mov r3, #0x0 @ clear for mrc call
|
||||
mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
|
||||
nop
|
||||
nop
|
||||
ldr r3, A_SDRC_POWER @ addr of sdrc power
|
||||
ldr r4, [r3] @ value of sdrc power
|
||||
orr r4, r4, #0x40 @ enable self refresh on idle req
|
||||
mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
|
||||
str r4, [r3] @ make it so
|
||||
mov r2, #0
|
||||
nop
|
||||
mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
|
||||
nop
|
||||
loop:
|
||||
subs r5, r5, #0x1 @ awake, wait just a bit
|
||||
bne loop
|
||||
|
||||
/* The DPLL has on before we take the DDR out of self refresh */
|
||||
bic r4, r4, #0x40 @ now clear self refresh bit.
|
||||
str r4, [r3] @ put vlaue back.
|
||||
ldr r4, A_SDRC0 @ make a clock happen
|
||||
ldr r4, [r4]
|
||||
nop @ start auto refresh only after clk ok
|
||||
movs r0, r0 @ see if DDR or SDR
|
||||
ldrne r1, A_SDRC_DLLA_CTRL_S @ get addr of DLL ctrl
|
||||
strne r0, [r1] @ rewrite DLLA to force DLL reload
|
||||
addne r1, r1, #0x8 @ move to DLLB
|
||||
strne r0, [r1] @ rewrite DLLB to force DLL reload
|
||||
|
||||
mov r5, #0x1000
|
||||
loop2:
|
||||
subs r5, r5, #0x1
|
||||
bne loop2
|
||||
/* resume*/
|
||||
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
|
||||
|
||||
A_SDRC_POWER:
|
||||
.word A_SDRC_POWER_V
|
||||
A_SDRC0:
|
||||
.word A_SDRC0_V
|
||||
A_CM_CLKSEL2_PLL_S:
|
||||
.word A_CM_CLKSEL2_PLL_V
|
||||
A_CM_CLKEN_PLL:
|
||||
.word A_CM_CLKEN_PLL_V
|
||||
A_SDRC_DLLA_CTRL_S:
|
||||
.word A_SDRC_DLLA_CTRL_V
|
||||
A_SDRC_MANUAL_S:
|
||||
.word A_SDRC_MANUAL_V
|
||||
|
||||
ENTRY(omap24xx_cpu_suspend_sz)
|
||||
.word . - omap24xx_cpu_suspend
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap1/sram.S
|
||||
* linux/arch/arm/mach-omap2/sram.S
|
||||
*
|
||||
* Omap2 specific functions that need to be run in internal SRAM
|
||||
*
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
#include <asm/arch/io.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#include <asm/arch/prcm.h>
|
||||
#include "prcm-regs.h"
|
||||
|
||||
#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
|
||||
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
#include <linux/pm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
|
|
|
|||
|
|
@ -16,24 +16,94 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/tlb.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <asm/arch/sram.h>
|
||||
#include <asm/arch/board.h>
|
||||
|
||||
#define OMAP1_SRAM_PA 0x20000000
|
||||
#define OMAP1_SRAM_VA 0xd0000000
|
||||
#define OMAP2_SRAM_PA 0x40200000
|
||||
#define OMAP2_SRAM_PUB_PA 0x4020f800
|
||||
#define OMAP2_SRAM_VA 0xd0000000
|
||||
#define OMAP2_SRAM_PUB_VA 0xd0000800
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP24XX)
|
||||
#define SRAM_BOOTLOADER_SZ 0x00
|
||||
#else
|
||||
#define SRAM_BOOTLOADER_SZ 0x80
|
||||
#endif
|
||||
|
||||
#define VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
|
||||
#define VA_READPERM0 IO_ADDRESS(0x68005050)
|
||||
#define VA_WRITEPERM0 IO_ADDRESS(0x68005058)
|
||||
#define VA_CONTROL_STAT IO_ADDRESS(0x480002F8)
|
||||
#define GP_DEVICE 0x300
|
||||
#define TYPE_MASK 0x700
|
||||
|
||||
#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
|
||||
|
||||
static unsigned long omap_sram_base;
|
||||
static unsigned long omap_sram_size;
|
||||
static unsigned long omap_sram_ceil;
|
||||
|
||||
unsigned long omap_fb_sram_start;
|
||||
unsigned long omap_fb_sram_size;
|
||||
|
||||
/* Depending on the target RAMFS firewall setup, the public usable amount of
|
||||
* SRAM varies. The default accessable size for all device types is 2k. A GP
|
||||
* device allows ARM11 but not other initators for full size. This
|
||||
* functionality seems ok until some nice security API happens.
|
||||
*/
|
||||
static int is_sram_locked(void)
|
||||
{
|
||||
int type = 0;
|
||||
|
||||
if (cpu_is_omap242x())
|
||||
type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK;
|
||||
|
||||
if (type == GP_DEVICE) {
|
||||
/* RAMFW: R/W access to all initators for all qualifier sets */
|
||||
if (cpu_is_omap242x()) {
|
||||
__raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */
|
||||
__raw_writel(0xCFDE, VA_READPERM0); /* all i-read */
|
||||
__raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */
|
||||
}
|
||||
return 0;
|
||||
} else
|
||||
return 1; /* assume locked with no PPA or security driver */
|
||||
}
|
||||
|
||||
void get_fb_sram_conf(unsigned long start_avail, unsigned size_avail,
|
||||
unsigned long *start, unsigned long *size)
|
||||
{
|
||||
const struct omap_fbmem_config *fbmem_conf;
|
||||
|
||||
fbmem_conf = omap_get_config(OMAP_TAG_FBMEM, struct omap_fbmem_config);
|
||||
if (fbmem_conf != NULL) {
|
||||
*start = fbmem_conf->fb_sram_start;
|
||||
*size = fbmem_conf->fb_sram_size;
|
||||
} else {
|
||||
*size = 0;
|
||||
*start = 0;
|
||||
}
|
||||
|
||||
if (*size && (
|
||||
*start < start_avail ||
|
||||
*start + *size > start_avail + size_avail)) {
|
||||
printk(KERN_ERR "invalid FB SRAM configuration\n");
|
||||
*start = start_avail;
|
||||
*size = size_avail;
|
||||
}
|
||||
|
||||
if (*size)
|
||||
pr_info("Reserving %lu bytes SRAM for frame buffer\n", *size);
|
||||
}
|
||||
|
||||
/*
|
||||
* The amount of SRAM depends on the core type.
|
||||
* Note that we cannot try to test for SRAM here because writes
|
||||
|
|
@ -42,26 +112,45 @@ static unsigned long omap_sram_ceil;
|
|||
*/
|
||||
void __init omap_detect_sram(void)
|
||||
{
|
||||
if (!cpu_is_omap24xx())
|
||||
unsigned long sram_start;
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
if (is_sram_locked()) {
|
||||
omap_sram_base = OMAP2_SRAM_PUB_VA;
|
||||
sram_start = OMAP2_SRAM_PUB_PA;
|
||||
omap_sram_size = 0x800; /* 2K */
|
||||
} else {
|
||||
omap_sram_base = OMAP2_SRAM_VA;
|
||||
sram_start = OMAP2_SRAM_PA;
|
||||
if (cpu_is_omap242x())
|
||||
omap_sram_size = 0xa0000; /* 640K */
|
||||
else if (cpu_is_omap243x())
|
||||
omap_sram_size = 0x10000; /* 64K */
|
||||
}
|
||||
} else {
|
||||
omap_sram_base = OMAP1_SRAM_VA;
|
||||
else
|
||||
omap_sram_base = OMAP2_SRAM_VA;
|
||||
sram_start = OMAP1_SRAM_PA;
|
||||
|
||||
if (cpu_is_omap730())
|
||||
omap_sram_size = 0x32000; /* 200K */
|
||||
else if (cpu_is_omap15xx())
|
||||
omap_sram_size = 0x30000; /* 192K */
|
||||
else if (cpu_is_omap1610() || cpu_is_omap1621() || cpu_is_omap1710())
|
||||
omap_sram_size = 0x4000; /* 16K */
|
||||
else if (cpu_is_omap1611())
|
||||
omap_sram_size = 0x3e800; /* 250K */
|
||||
else if (cpu_is_omap2420())
|
||||
omap_sram_size = 0xa0014; /* 640K */
|
||||
else {
|
||||
printk(KERN_ERR "Could not detect SRAM size\n");
|
||||
omap_sram_size = 0x4000;
|
||||
if (cpu_is_omap730())
|
||||
omap_sram_size = 0x32000; /* 200K */
|
||||
else if (cpu_is_omap15xx())
|
||||
omap_sram_size = 0x30000; /* 192K */
|
||||
else if (cpu_is_omap1610() || cpu_is_omap1621() ||
|
||||
cpu_is_omap1710())
|
||||
omap_sram_size = 0x4000; /* 16K */
|
||||
else if (cpu_is_omap1611())
|
||||
omap_sram_size = 0x3e800; /* 250K */
|
||||
else {
|
||||
printk(KERN_ERR "Could not detect SRAM size\n");
|
||||
omap_sram_size = 0x4000;
|
||||
}
|
||||
}
|
||||
|
||||
get_fb_sram_conf(sram_start + SRAM_BOOTLOADER_SZ,
|
||||
omap_sram_size - SRAM_BOOTLOADER_SZ,
|
||||
&omap_fb_sram_start, &omap_fb_sram_size);
|
||||
if (omap_fb_sram_size)
|
||||
omap_sram_size -= sram_start + omap_sram_size -
|
||||
omap_fb_sram_start;
|
||||
omap_sram_ceil = omap_sram_base + omap_sram_size;
|
||||
}
|
||||
|
||||
|
|
@ -80,12 +169,20 @@ static struct map_desc omap_sram_io_desc[] __initdata = {
|
|||
*/
|
||||
void __init omap_map_sram(void)
|
||||
{
|
||||
unsigned long base;
|
||||
|
||||
if (omap_sram_size == 0)
|
||||
return;
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
|
||||
omap_sram_io_desc[0].pfn = __phys_to_pfn(OMAP2_SRAM_PA);
|
||||
|
||||
if (is_sram_locked())
|
||||
base = OMAP2_SRAM_PUB_PA;
|
||||
else
|
||||
base = OMAP2_SRAM_PA;
|
||||
base = ROUND_DOWN(base, PAGE_SIZE);
|
||||
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
|
||||
}
|
||||
|
||||
omap_sram_io_desc[0].length = (omap_sram_size + PAGE_SIZE-1)/PAGE_SIZE;
|
||||
|
|
@ -93,7 +190,8 @@ void __init omap_map_sram(void)
|
|||
iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
|
||||
|
||||
printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
|
||||
omap_sram_io_desc[0].pfn, omap_sram_io_desc[0].virtual,
|
||||
__pfn_to_phys(omap_sram_io_desc[0].pfn),
|
||||
omap_sram_io_desc[0].virtual,
|
||||
omap_sram_io_desc[0].length);
|
||||
|
||||
/*
|
||||
|
|
@ -118,8 +216,9 @@ void * omap_sram_push(void * start, unsigned long size)
|
|||
printk(KERN_ERR "Not enough space in SRAM\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
omap_sram_ceil -= size;
|
||||
omap_sram_ceil &= ~0x3;
|
||||
omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
|
||||
memcpy((void *)omap_sram_ceil, start, size);
|
||||
|
||||
return (void *)omap_sram_ceil;
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@
|
|||
|
||||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* Powermanagement bitmasks
|
||||
* Power management bitmasks
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define IDLE_WAIT_CYCLES 0x00000fff
|
||||
|
|
@ -112,32 +112,59 @@
|
|||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
extern void prevent_idle_sleep(void);
|
||||
extern void allow_idle_sleep(void);
|
||||
|
||||
/**
|
||||
* clk_deny_idle - Prevents the clock from being idled during MPU idle
|
||||
* @clk: clock signal handle
|
||||
*/
|
||||
void clk_deny_idle(struct clk *clk);
|
||||
|
||||
/**
|
||||
* clk_allow_idle - Counters previous clk_deny_idle
|
||||
* @clk: clock signal handle
|
||||
*/
|
||||
void clk_deny_idle(struct clk *clk);
|
||||
|
||||
extern void omap_pm_idle(void);
|
||||
extern void omap_pm_suspend(void);
|
||||
extern void omap730_cpu_suspend(unsigned short, unsigned short);
|
||||
extern void omap1510_cpu_suspend(unsigned short, unsigned short);
|
||||
extern void omap1610_cpu_suspend(unsigned short, unsigned short);
|
||||
extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision);
|
||||
extern void omap730_idle_loop_suspend(void);
|
||||
extern void omap1510_idle_loop_suspend(void);
|
||||
extern void omap1610_idle_loop_suspend(void);
|
||||
extern void omap24xx_idle_loop_suspend(void);
|
||||
|
||||
extern unsigned int omap730_cpu_suspend_sz;
|
||||
extern unsigned int omap1510_cpu_suspend_sz;
|
||||
extern unsigned int omap1610_cpu_suspend_sz;
|
||||
extern unsigned int omap24xx_cpu_suspend_sz;
|
||||
extern unsigned int omap730_idle_loop_suspend_sz;
|
||||
extern unsigned int omap1510_idle_loop_suspend_sz;
|
||||
extern unsigned int omap1610_idle_loop_suspend_sz;
|
||||
extern unsigned int omap24xx_idle_loop_suspend_sz;
|
||||
|
||||
#ifdef CONFIG_OMAP_SERIAL_WAKE
|
||||
extern void omap_serial_wake_trigger(int enable);
|
||||
#else
|
||||
#define omap_serial_wakeup_init() {}
|
||||
#define omap_serial_wake_trigger(x) {}
|
||||
#endif /* CONFIG_OMAP_SERIAL_WAKE */
|
||||
|
||||
extern unsigned int omap730_cpu_suspend_sz;
|
||||
extern unsigned int omap730_idle_loop_suspend_sz;
|
||||
extern unsigned int omap1510_cpu_suspend_sz;
|
||||
extern unsigned int omap1510_idle_loop_suspend_sz;
|
||||
extern unsigned int omap1610_cpu_suspend_sz;
|
||||
extern unsigned int omap1610_idle_loop_suspend_sz;
|
||||
|
||||
#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
|
||||
#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
|
||||
#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
|
||||
|
||||
#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
|
||||
#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
|
||||
#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
|
||||
|
||||
#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
|
||||
#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
|
||||
#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
|
||||
|
|
@ -154,6 +181,10 @@ extern unsigned int omap1610_idle_loop_suspend_sz;
|
|||
#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
|
||||
#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
|
||||
|
||||
#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
|
||||
#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
|
||||
#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
|
||||
|
||||
/*
|
||||
* List of global OMAP registers to preserve.
|
||||
* More ones like CP and general purpose register values are preserved
|
||||
|
|
@ -176,6 +207,15 @@ enum arm_save_state {
|
|||
ARM_SLEEP_SAVE_SIZE
|
||||
};
|
||||
|
||||
enum dsp_save_state {
|
||||
DSP_SLEEP_SAVE_START = 0,
|
||||
/*
|
||||
* DSP registers 16 bits
|
||||
*/
|
||||
DSP_SLEEP_SAVE_DSP_IDLECT2,
|
||||
DSP_SLEEP_SAVE_SIZE
|
||||
};
|
||||
|
||||
enum ulpd_save_state {
|
||||
ULPD_SLEEP_SAVE_START = 0,
|
||||
/*
|
||||
|
|
@ -254,5 +294,30 @@ enum mpui1610_save_state {
|
|||
#endif
|
||||
};
|
||||
|
||||
enum omap24xx_save_state {
|
||||
OMAP24XX_SLEEP_SAVE_START = 0,
|
||||
OMAP24XX_SLEEP_SAVE_INTC_MIR0,
|
||||
OMAP24XX_SLEEP_SAVE_INTC_MIR1,
|
||||
OMAP24XX_SLEEP_SAVE_INTC_MIR2,
|
||||
OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
|
||||
OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
|
||||
OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
|
||||
OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
|
||||
OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
|
||||
OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
|
||||
OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
|
||||
OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
|
||||
OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
|
||||
OMAP24XX_SLEEP_SAVE_GPIO3_OE,
|
||||
OMAP24XX_SLEEP_SAVE_GPIO4_OE,
|
||||
OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
|
||||
OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
|
||||
OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
|
||||
OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
|
||||
OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
|
||||
OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
|
||||
OMAP24XX_SLEEP_SAVE_SIZE
|
||||
};
|
||||
|
||||
#endif /* ASSEMBLER */
|
||||
#endif /* __ASM_ARCH_OMAP_PM_H */
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
|
|||
u32 mem_type);
|
||||
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
|
||||
|
||||
extern unsigned long omap_fb_sram_start;
|
||||
extern unsigned long omap_fb_sram_size;
|
||||
|
||||
/* Do not use these */
|
||||
extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
|
||||
|
|
|
|||
Loading…
Reference in New Issue