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Some new clock ids for rk3188 and rk3368 as well as removal of a 

superfluous memory allocation error message.
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Merge tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull Rockchip clk drivers updates from Heiko Stuebner:

 - new clock ids for rk3188 and rk3368
 - removal of a superfluous memory allocation error message

* tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: use new cif/vdpu clock ids on rk3188
  clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
  clk: rockchip: add more rk3188 graphics clock ids
  clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs
  clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk()
This commit is contained in:
Stephen Boyd 2017-10-31 16:28:02 -07:00
parent b177571b9d 47e3ec0e4d
commit 6705fc9441
5 changed files with 15 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/rockchip/clk-cpu.c
View File

@ -322,8 +322,6 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
sizeof(*rates) * nrates,
GFP_KERNEL);
if (!cpuclk->rate_table) {
pr_err("%s: could not allocate memory for cpuclk rates\n",
__func__);
ret = -ENOMEM;
goto unregister_notifier;
}

12
drivers/clk/rockchip/clk-rk3188.c
View File

@ -290,15 +290,15 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 9, GFLAGS),
GATE(0, "hclk_vepu", "aclk_vepu", 0,
GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0,
RK2928_CLKGATE_CON(3), 10, GFLAGS),
COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 11, GFLAGS),
GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
@ -644,13 +644,13 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(5), 14, GFLAGS),
GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),

2
drivers/clk/rockchip/clk-rk3368.c
View File

@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
/*

9
include/dt-bindings/clock/rk3188-cru-common.h
View File

@ -68,12 +68,14 @@
#define ACLK_LCDC1 196
#define ACLK_GPU 197
#define ACLK_SMC 198
#define ACLK_CIF 199
#define ACLK_CIF1 199
#define ACLK_IPP 200
#define ACLK_RGA 201
#define ACLK_CIF0 202
#define ACLK_CPU 203
#define ACLK_PERI 204
#define ACLK_VEPU 205
#define ACLK_VDPU 206
/* pclk gates */
#define PCLK_GRF 320
@ -134,8 +136,11 @@
#define HCLK_NANDC0 467
#define HCLK_CPU 468
#define HCLK_PERI 469
#define HCLK_CIF1 470
#define HCLK_VEPU 471
#define HCLK_VDPU 472
#define CLK_NR_CLKS (HCLK_PERI + 1)
#define CLK_NR_CLKS (HCLK_VDPU + 1)
/* soft-reset indices */
#define SRST_MCORE 2

1
include/dt-bindings/clock/rk3368-cru.h
View File

@ -156,6 +156,7 @@
#define PCLK_ISP 366
#define PCLK_VIP 367
#define PCLK_WDT 368
#define PCLK_EFUSE256 369
/* hclk gates */
#define HCLK_SFC 448